1 // SPDX-License-Identifier: (GPL-2.0-only OR B 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2 // 2 //
3 // Copyright (c) 2022 Mediatek Corporation. Al 3 // Copyright (c) 2022 Mediatek Corporation. All rights reserved.
4 // 4 //
5 // Author: Allen-KH Cheng <allen-kh.cheng@medi 5 // Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
6 // Tinghan Shen <tinghan.shen@mediatek 6 // Tinghan Shen <tinghan.shen@mediatek.com>
7 // 7 //
8 // Hardware interface for mt8186 DSP code load 8 // Hardware interface for mt8186 DSP code loader
9 9
10 #include <sound/sof.h> 10 #include <sound/sof.h>
11 #include "mt8186.h" 11 #include "mt8186.h"
12 #include "../../ops.h" 12 #include "../../ops.h"
13 13
14 void mt8186_sof_hifixdsp_boot_sequence(struct 14 void mt8186_sof_hifixdsp_boot_sequence(struct snd_sof_dev *sdev, u32 boot_addr)
15 { 15 {
16 /* set RUNSTALL to stop core */ 16 /* set RUNSTALL to stop core */
17 snd_sof_dsp_update_bits(sdev, DSP_REG_ 17 snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, ADSP_HIFI_IO_CONFIG,
18 RUNSTALL, RUNS 18 RUNSTALL, RUNSTALL);
19 19
20 /* enable mbox 0 & 1 IRQ */ 20 /* enable mbox 0 & 1 IRQ */
21 snd_sof_dsp_update_bits(sdev, DSP_REG_ 21 snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, ADSP_MBOX_IRQ_EN,
22 DSP_MBOX0_IRQ_ 22 DSP_MBOX0_IRQ_EN | DSP_MBOX1_IRQ_EN,
23 DSP_MBOX0_IRQ_ 23 DSP_MBOX0_IRQ_EN | DSP_MBOX1_IRQ_EN);
24 24
25 /* set core boot address */ 25 /* set core boot address */
26 snd_sof_dsp_write(sdev, DSP_SECREG_BAR 26 snd_sof_dsp_write(sdev, DSP_SECREG_BAR, ADSP_ALTVEC_C0, boot_addr);
27 snd_sof_dsp_write(sdev, DSP_SECREG_BAR 27 snd_sof_dsp_write(sdev, DSP_SECREG_BAR, ADSP_ALTVECSEL, ADSP_ALTVECSEL_C0);
28 28
29 /* assert core reset */ 29 /* assert core reset */
30 snd_sof_dsp_update_bits(sdev, DSP_REG_ 30 snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, ADSP_CFGREG_SW_RSTN,
31 SW_RSTN_C0 | S 31 SW_RSTN_C0 | SW_DBG_RSTN_C0,
32 SW_RSTN_C0 | S 32 SW_RSTN_C0 | SW_DBG_RSTN_C0);
33 33
34 /* hardware requirement */ 34 /* hardware requirement */
35 udelay(1); 35 udelay(1);
36 36
37 /* release core reset */ 37 /* release core reset */
38 snd_sof_dsp_update_bits(sdev, DSP_REG_ 38 snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, ADSP_CFGREG_SW_RSTN,
39 SW_RSTN_C0 | S 39 SW_RSTN_C0 | SW_DBG_RSTN_C0,
40 0); 40 0);
41 41
42 /* clear RUNSTALL (bit31) to start cor 42 /* clear RUNSTALL (bit31) to start core */
43 snd_sof_dsp_update_bits(sdev, DSP_REG_ 43 snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, ADSP_HIFI_IO_CONFIG,
44 RUNSTALL, 0); 44 RUNSTALL, 0);
45 } 45 }
46 46
47 void mt8186_sof_hifixdsp_shutdown(struct snd_s 47 void mt8186_sof_hifixdsp_shutdown(struct snd_sof_dev *sdev)
48 { 48 {
49 /* set RUNSTALL to stop core */ 49 /* set RUNSTALL to stop core */
50 snd_sof_dsp_update_bits(sdev, DSP_REG_ 50 snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, ADSP_HIFI_IO_CONFIG,
51 RUNSTALL, RUNS 51 RUNSTALL, RUNSTALL);
52 52
53 /* assert core reset */ 53 /* assert core reset */
54 snd_sof_dsp_update_bits(sdev, DSP_REG_ 54 snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, ADSP_CFGREG_SW_RSTN,
55 SW_RSTN_C0 | S 55 SW_RSTN_C0 | SW_DBG_RSTN_C0,
56 SW_RSTN_C0 | S 56 SW_RSTN_C0 | SW_DBG_RSTN_C0);
57 } 57 }
58 58
59 59
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