1 // SPDX-License-Identifier: GPL-2.0-only <<
2 /* 1 /*
3 * STM32 ALSA SoC Digital Audio Interface (SAI 2 * STM32 ALSA SoC Digital Audio Interface (SAI) driver.
4 * 3 *
5 * Copyright (C) 2016, STMicroelectronics - Al 4 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
6 * Author(s): Olivier Moysan <olivier.moysan@s 5 * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics.
>> 6 *
>> 7 * License terms: GPL V2.0.
>> 8 *
>> 9 * This program is free software; you can redistribute it and/or modify it
>> 10 * under the terms of the GNU General Public License version 2 as published by
>> 11 * the Free Software Foundation.
>> 12 *
>> 13 * This program is distributed in the hope that it will be useful, but
>> 14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
>> 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
>> 16 * details.
7 */ 17 */
8 18
9 #include <linux/clk.h> 19 #include <linux/clk.h>
10 #include <linux/clk-provider.h> <<
11 #include <linux/kernel.h> 20 #include <linux/kernel.h>
12 #include <linux/module.h> 21 #include <linux/module.h>
13 #include <linux/of_irq.h> 22 #include <linux/of_irq.h>
14 #include <linux/of_platform.h> 23 #include <linux/of_platform.h>
15 #include <linux/pm_runtime.h> <<
16 #include <linux/regmap.h> 24 #include <linux/regmap.h>
17 25
18 #include <sound/asoundef.h> <<
19 #include <sound/core.h> 26 #include <sound/core.h>
20 #include <sound/dmaengine_pcm.h> 27 #include <sound/dmaengine_pcm.h>
21 #include <sound/pcm_params.h> 28 #include <sound/pcm_params.h>
22 29
23 #include "stm32_sai.h" 30 #include "stm32_sai.h"
24 31
25 #define SAI_FREE_PROTOCOL 0x0 32 #define SAI_FREE_PROTOCOL 0x0
26 #define SAI_SPDIF_PROTOCOL 0x1 <<
27 33
28 #define SAI_SLOT_SIZE_AUTO 0x0 34 #define SAI_SLOT_SIZE_AUTO 0x0
29 #define SAI_SLOT_SIZE_16 0x1 35 #define SAI_SLOT_SIZE_16 0x1
30 #define SAI_SLOT_SIZE_32 0x2 36 #define SAI_SLOT_SIZE_32 0x2
31 37
32 #define SAI_DATASIZE_8 0x2 38 #define SAI_DATASIZE_8 0x2
33 #define SAI_DATASIZE_10 0x3 39 #define SAI_DATASIZE_10 0x3
34 #define SAI_DATASIZE_16 0x4 40 #define SAI_DATASIZE_16 0x4
35 #define SAI_DATASIZE_20 0x5 41 #define SAI_DATASIZE_20 0x5
36 #define SAI_DATASIZE_24 0x6 42 #define SAI_DATASIZE_24 0x6
37 #define SAI_DATASIZE_32 0x7 43 #define SAI_DATASIZE_32 0x7
38 44
>> 45 #define STM_SAI_FIFO_SIZE 8
39 #define STM_SAI_DAI_NAME_SIZE 15 46 #define STM_SAI_DAI_NAME_SIZE 15
40 47
41 #define STM_SAI_IS_PLAYBACK(ip) ((ip)->dir == 48 #define STM_SAI_IS_PLAYBACK(ip) ((ip)->dir == SNDRV_PCM_STREAM_PLAYBACK)
42 #define STM_SAI_IS_CAPTURE(ip) ((ip)->dir == 49 #define STM_SAI_IS_CAPTURE(ip) ((ip)->dir == SNDRV_PCM_STREAM_CAPTURE)
43 50
44 #define STM_SAI_A_ID 0x0 51 #define STM_SAI_A_ID 0x0
45 #define STM_SAI_B_ID 0x1 52 #define STM_SAI_B_ID 0x1
46 53
47 #define STM_SAI_IS_SUB_A(x) ((x)->id == ST 54 #define STM_SAI_IS_SUB_A(x) ((x)->id == STM_SAI_A_ID)
48 !! 55 #define STM_SAI_IS_SUB_B(x) ((x)->id == STM_SAI_B_ID)
49 #define SAI_SYNC_NONE 0x0 !! 56 #define STM_SAI_BLOCK_NAME(x) (((x)->id == STM_SAI_A_ID) ? "A" : "B")
50 #define SAI_SYNC_INTERNAL 0x1 <<
51 #define SAI_SYNC_EXTERNAL 0x2 <<
52 <<
53 #define STM_SAI_PROTOCOL_IS_SPDIF(ip) ((ip)- <<
54 #define STM_SAI_HAS_SPDIF(x) ((x)->pdata->c <<
55 #define STM_SAI_HAS_PDM(x) ((x)->pdata->c <<
56 #define STM_SAI_HAS_EXT_SYNC(x) (!STM_SAI_IS_F <<
57 <<
58 #define SAI_IEC60958_BLOCK_FRAMES 192 <<
59 #define SAI_IEC60958_STATUS_BYTES 24 <<
60 <<
61 #define SAI_MCLK_NAME_LEN 32 <<
62 #define SAI_RATE_11K 11025 <<
63 57
64 /** 58 /**
65 * struct stm32_sai_sub_data - private data of 59 * struct stm32_sai_sub_data - private data of SAI sub block (block A or B)
66 * @pdev: device data pointer 60 * @pdev: device data pointer
67 * @regmap: SAI register map pointer 61 * @regmap: SAI register map pointer
68 * @regmap_config: SAI sub block register map 62 * @regmap_config: SAI sub block register map configuration pointer
69 * @dma_params: dma configuration data for rx 63 * @dma_params: dma configuration data for rx or tx channel
70 * @cpu_dai_drv: DAI driver data pointer 64 * @cpu_dai_drv: DAI driver data pointer
71 * @cpu_dai: DAI runtime data pointer 65 * @cpu_dai: DAI runtime data pointer
72 * @substream: PCM substream data pointer 66 * @substream: PCM substream data pointer
73 * @pdata: SAI block parent data pointer 67 * @pdata: SAI block parent data pointer
74 * @np_sync_provider: synchronization provider <<
75 * @sai_ck: kernel clock feeding the SAI clock 68 * @sai_ck: kernel clock feeding the SAI clock generator
76 * @sai_mclk: master clock from SAI mclk provi <<
77 * @phys_addr: SAI registers physical base add 69 * @phys_addr: SAI registers physical base address
78 * @mclk_rate: SAI block master clock frequenc 70 * @mclk_rate: SAI block master clock frequency (Hz). set at init
79 * @id: SAI sub block id corresponding to sub- 71 * @id: SAI sub block id corresponding to sub-block A or B
80 * @dir: SAI block direction (playback or capt 72 * @dir: SAI block direction (playback or capture). set at init
81 * @master: SAI block mode flag. (true=master, 73 * @master: SAI block mode flag. (true=master, false=slave) set at init
82 * @spdif: SAI S/PDIF iec60958 mode flag. set <<
83 * @fmt: SAI block format. relevant only for c 74 * @fmt: SAI block format. relevant only for custom protocols. set at init
84 * @sync: SAI block synchronization mode. (non 75 * @sync: SAI block synchronization mode. (none, internal or external)
85 * @synco: SAI block ext sync source (provider <<
86 * @synci: SAI block ext sync source (client s <<
87 * @fs_length: frame synchronization length. d 76 * @fs_length: frame synchronization length. depends on protocol settings
88 * @slots: rx or tx slot number 77 * @slots: rx or tx slot number
89 * @slot_width: rx or tx slot width in bits 78 * @slot_width: rx or tx slot width in bits
90 * @slot_mask: rx or tx active slots mask. set 79 * @slot_mask: rx or tx active slots mask. set at init or at runtime
91 * @data_size: PCM data width. corresponds to 80 * @data_size: PCM data width. corresponds to PCM substream width.
92 * @spdif_frm_cnt: S/PDIF playback frame count <<
93 * @iec958: iec958 data <<
94 * @ctrl_lock: control lock <<
95 * @irq_lock: prevent race condition with IRQ <<
96 */ 81 */
97 struct stm32_sai_sub_data { 82 struct stm32_sai_sub_data {
98 struct platform_device *pdev; 83 struct platform_device *pdev;
99 struct regmap *regmap; 84 struct regmap *regmap;
100 const struct regmap_config *regmap_con 85 const struct regmap_config *regmap_config;
101 struct snd_dmaengine_dai_dma_data dma_ 86 struct snd_dmaengine_dai_dma_data dma_params;
102 struct snd_soc_dai_driver cpu_dai_drv; !! 87 struct snd_soc_dai_driver *cpu_dai_drv;
103 struct snd_soc_dai *cpu_dai; 88 struct snd_soc_dai *cpu_dai;
104 struct snd_pcm_substream *substream; 89 struct snd_pcm_substream *substream;
105 struct stm32_sai_data *pdata; 90 struct stm32_sai_data *pdata;
106 struct device_node *np_sync_provider; <<
107 struct clk *sai_ck; 91 struct clk *sai_ck;
108 struct clk *sai_mclk; <<
109 dma_addr_t phys_addr; 92 dma_addr_t phys_addr;
110 unsigned int mclk_rate; 93 unsigned int mclk_rate;
111 unsigned int id; 94 unsigned int id;
112 int dir; 95 int dir;
113 bool master; 96 bool master;
114 bool spdif; <<
115 int fmt; 97 int fmt;
116 int sync; 98 int sync;
117 int synco; <<
118 int synci; <<
119 int fs_length; 99 int fs_length;
120 int slots; 100 int slots;
121 int slot_width; 101 int slot_width;
122 int slot_mask; 102 int slot_mask;
123 int data_size; 103 int data_size;
124 unsigned int spdif_frm_cnt; <<
125 struct snd_aes_iec958 iec958; <<
126 struct mutex ctrl_lock; /* protect res <<
127 spinlock_t irq_lock; /* used to preven <<
128 }; 104 };
129 105
130 enum stm32_sai_fifo_th { 106 enum stm32_sai_fifo_th {
131 STM_SAI_FIFO_TH_EMPTY, 107 STM_SAI_FIFO_TH_EMPTY,
132 STM_SAI_FIFO_TH_QUARTER, 108 STM_SAI_FIFO_TH_QUARTER,
133 STM_SAI_FIFO_TH_HALF, 109 STM_SAI_FIFO_TH_HALF,
134 STM_SAI_FIFO_TH_3_QUARTER, 110 STM_SAI_FIFO_TH_3_QUARTER,
135 STM_SAI_FIFO_TH_FULL, 111 STM_SAI_FIFO_TH_FULL,
136 }; 112 };
137 113
138 static bool stm32_sai_sub_readable_reg(struct 114 static bool stm32_sai_sub_readable_reg(struct device *dev, unsigned int reg)
139 { 115 {
140 switch (reg) { 116 switch (reg) {
141 case STM_SAI_CR1_REGX: 117 case STM_SAI_CR1_REGX:
142 case STM_SAI_CR2_REGX: 118 case STM_SAI_CR2_REGX:
143 case STM_SAI_FRCR_REGX: 119 case STM_SAI_FRCR_REGX:
144 case STM_SAI_SLOTR_REGX: 120 case STM_SAI_SLOTR_REGX:
145 case STM_SAI_IMR_REGX: 121 case STM_SAI_IMR_REGX:
146 case STM_SAI_SR_REGX: 122 case STM_SAI_SR_REGX:
147 case STM_SAI_CLRFR_REGX: 123 case STM_SAI_CLRFR_REGX:
148 case STM_SAI_DR_REGX: 124 case STM_SAI_DR_REGX:
149 case STM_SAI_PDMCR_REGX: 125 case STM_SAI_PDMCR_REGX:
150 case STM_SAI_PDMLY_REGX: 126 case STM_SAI_PDMLY_REGX:
151 return true; 127 return true;
152 default: 128 default:
153 return false; 129 return false;
154 } 130 }
155 } 131 }
156 132
157 static bool stm32_sai_sub_volatile_reg(struct 133 static bool stm32_sai_sub_volatile_reg(struct device *dev, unsigned int reg)
158 { 134 {
159 switch (reg) { 135 switch (reg) {
160 case STM_SAI_DR_REGX: 136 case STM_SAI_DR_REGX:
161 case STM_SAI_SR_REGX: <<
162 return true; 137 return true;
163 default: 138 default:
164 return false; 139 return false;
165 } 140 }
166 } 141 }
167 142
168 static bool stm32_sai_sub_writeable_reg(struct 143 static bool stm32_sai_sub_writeable_reg(struct device *dev, unsigned int reg)
169 { 144 {
170 switch (reg) { 145 switch (reg) {
171 case STM_SAI_CR1_REGX: 146 case STM_SAI_CR1_REGX:
172 case STM_SAI_CR2_REGX: 147 case STM_SAI_CR2_REGX:
173 case STM_SAI_FRCR_REGX: 148 case STM_SAI_FRCR_REGX:
174 case STM_SAI_SLOTR_REGX: 149 case STM_SAI_SLOTR_REGX:
175 case STM_SAI_IMR_REGX: 150 case STM_SAI_IMR_REGX:
>> 151 case STM_SAI_SR_REGX:
176 case STM_SAI_CLRFR_REGX: 152 case STM_SAI_CLRFR_REGX:
177 case STM_SAI_DR_REGX: 153 case STM_SAI_DR_REGX:
178 case STM_SAI_PDMCR_REGX: 154 case STM_SAI_PDMCR_REGX:
179 case STM_SAI_PDMLY_REGX: 155 case STM_SAI_PDMLY_REGX:
180 return true; 156 return true;
181 default: 157 default:
182 return false; 158 return false;
183 } 159 }
184 } 160 }
185 161
186 static int stm32_sai_sub_reg_up(struct stm32_s <<
187 unsigned int r <<
188 unsigned int v <<
189 { <<
190 int ret; <<
191 <<
192 ret = clk_enable(sai->pdata->pclk); <<
193 if (ret < 0) <<
194 return ret; <<
195 <<
196 ret = regmap_update_bits(sai->regmap, <<
197 <<
198 clk_disable(sai->pdata->pclk); <<
199 <<
200 return ret; <<
201 } <<
202 <<
203 static int stm32_sai_sub_reg_wr(struct stm32_s <<
204 unsigned int r <<
205 unsigned int v <<
206 { <<
207 int ret; <<
208 <<
209 ret = clk_enable(sai->pdata->pclk); <<
210 if (ret < 0) <<
211 return ret; <<
212 <<
213 ret = regmap_write_bits(sai->regmap, r <<
214 <<
215 clk_disable(sai->pdata->pclk); <<
216 <<
217 return ret; <<
218 } <<
219 <<
220 static int stm32_sai_sub_reg_rd(struct stm32_s <<
221 unsigned int r <<
222 { <<
223 int ret; <<
224 <<
225 ret = clk_enable(sai->pdata->pclk); <<
226 if (ret < 0) <<
227 return ret; <<
228 <<
229 ret = regmap_read(sai->regmap, reg, va <<
230 <<
231 clk_disable(sai->pdata->pclk); <<
232 <<
233 return ret; <<
234 } <<
235 <<
236 static const struct regmap_config stm32_sai_su 162 static const struct regmap_config stm32_sai_sub_regmap_config_f4 = {
237 .reg_bits = 32, 163 .reg_bits = 32,
238 .reg_stride = 4, 164 .reg_stride = 4,
239 .val_bits = 32, 165 .val_bits = 32,
240 .max_register = STM_SAI_DR_REGX, 166 .max_register = STM_SAI_DR_REGX,
241 .readable_reg = stm32_sai_sub_readable 167 .readable_reg = stm32_sai_sub_readable_reg,
242 .volatile_reg = stm32_sai_sub_volatile 168 .volatile_reg = stm32_sai_sub_volatile_reg,
243 .writeable_reg = stm32_sai_sub_writeab 169 .writeable_reg = stm32_sai_sub_writeable_reg,
244 .fast_io = true, 170 .fast_io = true,
245 .cache_type = REGCACHE_FLAT, <<
246 }; 171 };
247 172
248 static const struct regmap_config stm32_sai_su 173 static const struct regmap_config stm32_sai_sub_regmap_config_h7 = {
249 .reg_bits = 32, 174 .reg_bits = 32,
250 .reg_stride = 4, 175 .reg_stride = 4,
251 .val_bits = 32, 176 .val_bits = 32,
252 .max_register = STM_SAI_PDMLY_REGX, 177 .max_register = STM_SAI_PDMLY_REGX,
253 .readable_reg = stm32_sai_sub_readable 178 .readable_reg = stm32_sai_sub_readable_reg,
254 .volatile_reg = stm32_sai_sub_volatile 179 .volatile_reg = stm32_sai_sub_volatile_reg,
255 .writeable_reg = stm32_sai_sub_writeab 180 .writeable_reg = stm32_sai_sub_writeable_reg,
256 .fast_io = true, 181 .fast_io = true,
257 .cache_type = REGCACHE_FLAT, <<
258 }; <<
259 <<
260 static int snd_pcm_iec958_info(struct snd_kcon <<
261 struct snd_ctl_ <<
262 { <<
263 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC9 <<
264 uinfo->count = 1; <<
265 <<
266 return 0; <<
267 } <<
268 <<
269 static int snd_pcm_iec958_get(struct snd_kcont <<
270 struct snd_ctl_e <<
271 { <<
272 struct stm32_sai_sub_data *sai = snd_k <<
273 <<
274 mutex_lock(&sai->ctrl_lock); <<
275 memcpy(uctl->value.iec958.status, sai- <<
276 mutex_unlock(&sai->ctrl_lock); <<
277 <<
278 return 0; <<
279 } <<
280 <<
281 static int snd_pcm_iec958_put(struct snd_kcont <<
282 struct snd_ctl_e <<
283 { <<
284 struct stm32_sai_sub_data *sai = snd_k <<
285 <<
286 mutex_lock(&sai->ctrl_lock); <<
287 memcpy(sai->iec958.status, uctl->value <<
288 mutex_unlock(&sai->ctrl_lock); <<
289 <<
290 return 0; <<
291 } <<
292 <<
293 static const struct snd_kcontrol_new iec958_ct <<
294 .access = (SNDRV_CTL_ELEM_ACCESS_READW <<
295 SNDRV_CTL_ELEM_ACCESS_ <<
296 .iface = SNDRV_CTL_ELEM_IFACE_PCM, <<
297 .name = SNDRV_CTL_NAME_IEC958("", PLAY <<
298 .info = snd_pcm_iec958_info, <<
299 .get = snd_pcm_iec958_get, <<
300 .put = snd_pcm_iec958_put, <<
301 }; <<
302 <<
303 struct stm32_sai_mclk_data { <<
304 struct clk_hw hw; <<
305 unsigned long freq; <<
306 struct stm32_sai_sub_data *sai_data; <<
307 }; <<
308 <<
309 #define to_mclk_data(_hw) container_of(_hw, st <<
310 #define STM32_SAI_MAX_CLKS 1 <<
311 <<
312 static int stm32_sai_get_clk_div(struct stm32_ <<
313 unsigned long <<
314 unsigned long <<
315 { <<
316 int version = sai->pdata->conf.version <<
317 int div; <<
318 <<
319 div = DIV_ROUND_CLOSEST(input_rate, ou <<
320 if (div > SAI_XCR1_MCKDIV_MAX(version) <<
321 dev_err(&sai->pdev->dev, "Divi <<
322 return -EINVAL; <<
323 } <<
324 dev_dbg(&sai->pdev->dev, "SAI divider <<
325 <<
326 if (input_rate % div) <<
327 dev_dbg(&sai->pdev->dev, <<
328 "Rate not accurate. re <<
329 output_rate, input_rat <<
330 <<
331 return div; <<
332 } <<
333 <<
334 static int stm32_sai_set_clk_div(struct stm32_ <<
335 unsigned int <<
336 { <<
337 int version = sai->pdata->conf.version <<
338 int ret, cr1, mask; <<
339 <<
340 if (div > SAI_XCR1_MCKDIV_MAX(version) <<
341 dev_err(&sai->pdev->dev, "Divi <<
342 return -EINVAL; <<
343 } <<
344 <<
345 mask = SAI_XCR1_MCKDIV_MASK(SAI_XCR1_M <<
346 cr1 = SAI_XCR1_MCKDIV_SET(div); <<
347 ret = stm32_sai_sub_reg_up(sai, STM_SA <<
348 if (ret < 0) <<
349 dev_err(&sai->pdev->dev, "Fail <<
350 <<
351 return ret; <<
352 } <<
353 <<
354 static int stm32_sai_set_parent_clock(struct s <<
355 unsigned <<
356 { <<
357 struct platform_device *pdev = sai->pd <<
358 struct clk *parent_clk = sai->pdata->c <<
359 int ret; <<
360 <<
361 if (!(rate % SAI_RATE_11K)) <<
362 parent_clk = sai->pdata->clk_x <<
363 <<
364 ret = clk_set_parent(sai->sai_ck, pare <<
365 if (ret) <<
366 dev_err(&pdev->dev, " Error %d <<
367 ret, ret == -EBUSY ? <<
368 "Active stream rates c <<
369 <<
370 return ret; <<
371 } <<
372 <<
373 static long stm32_sai_mclk_round_rate(struct c <<
374 unsigned <<
375 { <<
376 struct stm32_sai_mclk_data *mclk = to_ <<
377 struct stm32_sai_sub_data *sai = mclk- <<
378 int div; <<
379 <<
380 div = stm32_sai_get_clk_div(sai, *prat <<
381 if (div <= 0) <<
382 return -EINVAL; <<
383 <<
384 mclk->freq = *prate / div; <<
385 <<
386 return mclk->freq; <<
387 } <<
388 <<
389 static unsigned long stm32_sai_mclk_recalc_rat <<
390 <<
391 { <<
392 struct stm32_sai_mclk_data *mclk = to_ <<
393 <<
394 return mclk->freq; <<
395 } <<
396 <<
397 static int stm32_sai_mclk_set_rate(struct clk_ <<
398 unsigned lo <<
399 { <<
400 struct stm32_sai_mclk_data *mclk = to_ <<
401 struct stm32_sai_sub_data *sai = mclk- <<
402 int div, ret; <<
403 <<
404 div = stm32_sai_get_clk_div(sai, paren <<
405 if (div < 0) <<
406 return div; <<
407 <<
408 ret = stm32_sai_set_clk_div(sai, div); <<
409 if (ret) <<
410 return ret; <<
411 <<
412 mclk->freq = rate; <<
413 <<
414 return 0; <<
415 } <<
416 <<
417 static int stm32_sai_mclk_enable(struct clk_hw <<
418 { <<
419 struct stm32_sai_mclk_data *mclk = to_ <<
420 struct stm32_sai_sub_data *sai = mclk- <<
421 <<
422 dev_dbg(&sai->pdev->dev, "Enable maste <<
423 <<
424 return stm32_sai_sub_reg_up(sai, STM_S <<
425 SAI_XCR1_M <<
426 } <<
427 <<
428 static void stm32_sai_mclk_disable(struct clk_ <<
429 { <<
430 struct stm32_sai_mclk_data *mclk = to_ <<
431 struct stm32_sai_sub_data *sai = mclk- <<
432 <<
433 dev_dbg(&sai->pdev->dev, "Disable mast <<
434 <<
435 stm32_sai_sub_reg_up(sai, STM_SAI_CR1_ <<
436 } <<
437 <<
438 static const struct clk_ops mclk_ops = { <<
439 .enable = stm32_sai_mclk_enable, <<
440 .disable = stm32_sai_mclk_disable, <<
441 .recalc_rate = stm32_sai_mclk_recalc_r <<
442 .round_rate = stm32_sai_mclk_round_rat <<
443 .set_rate = stm32_sai_mclk_set_rate, <<
444 }; 182 };
445 183
446 static int stm32_sai_add_mclk_provider(struct <<
447 { <<
448 struct clk_hw *hw; <<
449 struct stm32_sai_mclk_data *mclk; <<
450 struct device *dev = &sai->pdev->dev; <<
451 const char *pname = __clk_get_name(sai <<
452 char *mclk_name, *p, *s = (char *)pnam <<
453 int ret, i = 0; <<
454 <<
455 mclk = devm_kzalloc(dev, sizeof(*mclk) <<
456 if (!mclk) <<
457 return -ENOMEM; <<
458 <<
459 mclk_name = devm_kcalloc(dev, sizeof(c <<
460 SAI_MCLK_NAME <<
461 if (!mclk_name) <<
462 return -ENOMEM; <<
463 <<
464 /* <<
465 * Forge mclk clock name from parent c <<
466 * String after "_" char is stripped i <<
467 */ <<
468 p = mclk_name; <<
469 while (*s && *s != '_' && (i < (SAI_MC <<
470 *p++ = *s++; <<
471 i++; <<
472 } <<
473 STM_SAI_IS_SUB_A(sai) ? strcat(p, "a_m <<
474 <<
475 mclk->hw.init = CLK_HW_INIT(mclk_name, <<
476 mclk->sai_data = sai; <<
477 hw = &mclk->hw; <<
478 <<
479 dev_dbg(dev, "Register master clock %s <<
480 ret = devm_clk_hw_register(&sai->pdev- <<
481 if (ret) { <<
482 dev_err(dev, "mclk register re <<
483 return ret; <<
484 } <<
485 sai->sai_mclk = hw->clk; <<
486 <<
487 /* register mclk provider */ <<
488 return devm_of_clk_add_hw_provider(dev <<
489 } <<
490 <<
491 static irqreturn_t stm32_sai_isr(int irq, void 184 static irqreturn_t stm32_sai_isr(int irq, void *devid)
492 { 185 {
493 struct stm32_sai_sub_data *sai = (stru 186 struct stm32_sai_sub_data *sai = (struct stm32_sai_sub_data *)devid;
>> 187 struct snd_pcm_substream *substream = sai->substream;
494 struct platform_device *pdev = sai->pd 188 struct platform_device *pdev = sai->pdev;
495 unsigned int sr, imr, flags; 189 unsigned int sr, imr, flags;
496 snd_pcm_state_t status = SNDRV_PCM_STA 190 snd_pcm_state_t status = SNDRV_PCM_STATE_RUNNING;
497 191
498 stm32_sai_sub_reg_rd(sai, STM_SAI_IMR_ !! 192 regmap_read(sai->regmap, STM_SAI_IMR_REGX, &imr);
499 stm32_sai_sub_reg_rd(sai, STM_SAI_SR_R !! 193 regmap_read(sai->regmap, STM_SAI_SR_REGX, &sr);
500 194
501 flags = sr & imr; 195 flags = sr & imr;
502 if (!flags) 196 if (!flags)
503 return IRQ_NONE; 197 return IRQ_NONE;
504 198
505 stm32_sai_sub_reg_wr(sai, STM_SAI_CLRF !! 199 regmap_update_bits(sai->regmap, STM_SAI_CLRFR_REGX, SAI_XCLRFR_MASK,
506 SAI_XCLRFR_MASK); !! 200 SAI_XCLRFR_MASK);
507 <<
508 if (!sai->substream) { <<
509 dev_err(&pdev->dev, "Device st <<
510 return IRQ_NONE; <<
511 } <<
512 201
513 if (flags & SAI_XIMR_OVRUDRIE) { 202 if (flags & SAI_XIMR_OVRUDRIE) {
514 dev_err(&pdev->dev, "IRQ %s\n" 203 dev_err(&pdev->dev, "IRQ %s\n",
515 STM_SAI_IS_PLAYBACK(sa 204 STM_SAI_IS_PLAYBACK(sai) ? "underrun" : "overrun");
516 status = SNDRV_PCM_STATE_XRUN; 205 status = SNDRV_PCM_STATE_XRUN;
517 } 206 }
518 207
519 if (flags & SAI_XIMR_MUTEDETIE) 208 if (flags & SAI_XIMR_MUTEDETIE)
520 dev_dbg(&pdev->dev, "IRQ mute 209 dev_dbg(&pdev->dev, "IRQ mute detected\n");
521 210
522 if (flags & SAI_XIMR_WCKCFGIE) { 211 if (flags & SAI_XIMR_WCKCFGIE) {
523 dev_err(&pdev->dev, "IRQ wrong 212 dev_err(&pdev->dev, "IRQ wrong clock configuration\n");
524 status = SNDRV_PCM_STATE_DISCO 213 status = SNDRV_PCM_STATE_DISCONNECTED;
525 } 214 }
526 215
527 if (flags & SAI_XIMR_CNRDYIE) 216 if (flags & SAI_XIMR_CNRDYIE)
528 dev_err(&pdev->dev, "IRQ Codec 217 dev_err(&pdev->dev, "IRQ Codec not ready\n");
529 218
530 if (flags & SAI_XIMR_AFSDETIE) { 219 if (flags & SAI_XIMR_AFSDETIE) {
531 dev_err(&pdev->dev, "IRQ Antic 220 dev_err(&pdev->dev, "IRQ Anticipated frame synchro\n");
532 status = SNDRV_PCM_STATE_XRUN; 221 status = SNDRV_PCM_STATE_XRUN;
533 } 222 }
534 223
535 if (flags & SAI_XIMR_LFSDETIE) { 224 if (flags & SAI_XIMR_LFSDETIE) {
536 dev_err(&pdev->dev, "IRQ Late 225 dev_err(&pdev->dev, "IRQ Late frame synchro\n");
537 status = SNDRV_PCM_STATE_XRUN; 226 status = SNDRV_PCM_STATE_XRUN;
538 } 227 }
539 228
540 spin_lock(&sai->irq_lock); !! 229 if (status != SNDRV_PCM_STATE_RUNNING) {
541 if (status != SNDRV_PCM_STATE_RUNNING !! 230 snd_pcm_stream_lock(substream);
542 snd_pcm_stop_xrun(sai->substre !! 231 snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
543 spin_unlock(&sai->irq_lock); !! 232 snd_pcm_stream_unlock(substream);
>> 233 }
544 234
545 return IRQ_HANDLED; 235 return IRQ_HANDLED;
546 } 236 }
547 237
548 static int stm32_sai_set_sysclk(struct snd_soc 238 static int stm32_sai_set_sysclk(struct snd_soc_dai *cpu_dai,
549 int clk_id, un 239 int clk_id, unsigned int freq, int dir)
550 { 240 {
551 struct stm32_sai_sub_data *sai = snd_s 241 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
552 int ret; 242 int ret;
553 243
554 if (dir == SND_SOC_CLOCK_OUT && sai->s !! 244 if ((dir == SND_SOC_CLOCK_OUT) && sai->master) {
555 ret = stm32_sai_sub_reg_up(sai !! 245 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX,
556 SAI !! 246 SAI_XCR1_NODIV,
557 freq !! 247 (unsigned int)~SAI_XCR1_NODIV);
558 if (ret < 0) 248 if (ret < 0)
559 return ret; 249 return ret;
560 250
561 /* Assume shutdown if requeste <<
562 if (!freq) { <<
563 /* Release mclk rate o <<
564 if (sai->mclk_rate) { <<
565 clk_rate_exclu <<
566 sai->mclk_rate <<
567 } <<
568 return 0; <<
569 } <<
570 <<
571 /* If master clock is used, se <<
572 ret = stm32_sai_set_parent_clo <<
573 if (ret) <<
574 return ret; <<
575 <<
576 ret = clk_set_rate_exclusive(s <<
577 if (ret) { <<
578 dev_err(cpu_dai->dev, <<
579 ret == -EBUSY <<
580 "Active stream <<
581 "Could not set <<
582 return ret; <<
583 } <<
584 <<
585 dev_dbg(cpu_dai->dev, "SAI MCL <<
586 sai->mclk_rate = freq; 251 sai->mclk_rate = freq;
>> 252 dev_dbg(cpu_dai->dev, "SAI MCLK frequency is %uHz\n", freq);
587 } 253 }
588 254
589 return 0; 255 return 0;
590 } 256 }
591 257
592 static int stm32_sai_set_dai_tdm_slot(struct s 258 static int stm32_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
593 u32 rx_m 259 u32 rx_mask, int slots, int slot_width)
594 { 260 {
595 struct stm32_sai_sub_data *sai = snd_s 261 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
596 int slotr, slotr_mask, slot_size; 262 int slotr, slotr_mask, slot_size;
597 263
598 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { <<
599 dev_warn(cpu_dai->dev, "Slot s <<
600 return 0; <<
601 } <<
602 <<
603 dev_dbg(cpu_dai->dev, "Masks tx/rx:%#x 264 dev_dbg(cpu_dai->dev, "Masks tx/rx:%#x/%#x, slots:%d, width:%d\n",
604 tx_mask, rx_mask, slots, slot_ 265 tx_mask, rx_mask, slots, slot_width);
605 266
606 switch (slot_width) { 267 switch (slot_width) {
607 case 16: 268 case 16:
608 slot_size = SAI_SLOT_SIZE_16; 269 slot_size = SAI_SLOT_SIZE_16;
609 break; 270 break;
610 case 32: 271 case 32:
611 slot_size = SAI_SLOT_SIZE_32; 272 slot_size = SAI_SLOT_SIZE_32;
612 break; 273 break;
613 default: 274 default:
614 slot_size = SAI_SLOT_SIZE_AUTO 275 slot_size = SAI_SLOT_SIZE_AUTO;
615 break; 276 break;
616 } 277 }
617 278
618 slotr = SAI_XSLOTR_SLOTSZ_SET(slot_siz 279 slotr = SAI_XSLOTR_SLOTSZ_SET(slot_size) |
619 SAI_XSLOTR_NBSLOT_SET(slots - 280 SAI_XSLOTR_NBSLOT_SET(slots - 1);
620 slotr_mask = SAI_XSLOTR_SLOTSZ_MASK | 281 slotr_mask = SAI_XSLOTR_SLOTSZ_MASK | SAI_XSLOTR_NBSLOT_MASK;
621 282
622 /* tx/rx mask set in machine init, if 283 /* tx/rx mask set in machine init, if slot number defined in DT */
623 if (STM_SAI_IS_PLAYBACK(sai)) { 284 if (STM_SAI_IS_PLAYBACK(sai)) {
624 sai->slot_mask = tx_mask; 285 sai->slot_mask = tx_mask;
625 slotr |= SAI_XSLOTR_SLOTEN_SET 286 slotr |= SAI_XSLOTR_SLOTEN_SET(tx_mask);
626 } 287 }
627 288
628 if (STM_SAI_IS_CAPTURE(sai)) { 289 if (STM_SAI_IS_CAPTURE(sai)) {
629 sai->slot_mask = rx_mask; 290 sai->slot_mask = rx_mask;
630 slotr |= SAI_XSLOTR_SLOTEN_SET 291 slotr |= SAI_XSLOTR_SLOTEN_SET(rx_mask);
631 } 292 }
632 293
633 slotr_mask |= SAI_XSLOTR_SLOTEN_MASK; 294 slotr_mask |= SAI_XSLOTR_SLOTEN_MASK;
634 295
635 stm32_sai_sub_reg_up(sai, STM_SAI_SLOT !! 296 regmap_update_bits(sai->regmap, STM_SAI_SLOTR_REGX, slotr_mask, slotr);
636 297
637 sai->slot_width = slot_width; 298 sai->slot_width = slot_width;
638 sai->slots = slots; 299 sai->slots = slots;
639 300
640 return 0; 301 return 0;
641 } 302 }
642 303
643 static int stm32_sai_set_dai_fmt(struct snd_so 304 static int stm32_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
644 { 305 {
645 struct stm32_sai_sub_data *sai = snd_s 306 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
646 int cr1, frcr = 0; !! 307 int cr1 = 0, frcr = 0;
647 int cr1_mask, frcr_mask = 0; !! 308 int cr1_mask = 0, frcr_mask = 0;
648 int ret; 309 int ret;
649 310
650 dev_dbg(cpu_dai->dev, "fmt %x\n", fmt) 311 dev_dbg(cpu_dai->dev, "fmt %x\n", fmt);
651 312
652 /* Do not generate master by default * <<
653 cr1 = SAI_XCR1_NODIV; <<
654 cr1_mask = SAI_XCR1_NODIV; <<
655 <<
656 cr1_mask |= SAI_XCR1_PRTCFG_MASK; <<
657 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { <<
658 cr1 |= SAI_XCR1_PRTCFG_SET(SAI <<
659 goto conf_update; <<
660 } <<
661 <<
662 cr1 |= SAI_XCR1_PRTCFG_SET(SAI_FREE_PR <<
663 <<
664 switch (fmt & SND_SOC_DAIFMT_FORMAT_MA 313 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
665 /* SCK active high for all protocols * 314 /* SCK active high for all protocols */
666 case SND_SOC_DAIFMT_I2S: 315 case SND_SOC_DAIFMT_I2S:
667 cr1 |= SAI_XCR1_CKSTR; 316 cr1 |= SAI_XCR1_CKSTR;
668 frcr |= SAI_XFRCR_FSOFF | SAI_ 317 frcr |= SAI_XFRCR_FSOFF | SAI_XFRCR_FSDEF;
669 break; 318 break;
670 /* Left justified */ 319 /* Left justified */
671 case SND_SOC_DAIFMT_MSB: 320 case SND_SOC_DAIFMT_MSB:
672 frcr |= SAI_XFRCR_FSPOL | SAI_ 321 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF;
673 break; 322 break;
674 /* Right justified */ 323 /* Right justified */
675 case SND_SOC_DAIFMT_LSB: 324 case SND_SOC_DAIFMT_LSB:
676 frcr |= SAI_XFRCR_FSPOL | SAI_ 325 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF;
677 break; 326 break;
678 case SND_SOC_DAIFMT_DSP_A: 327 case SND_SOC_DAIFMT_DSP_A:
679 frcr |= SAI_XFRCR_FSPOL | SAI_ 328 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF;
680 break; 329 break;
681 case SND_SOC_DAIFMT_DSP_B: 330 case SND_SOC_DAIFMT_DSP_B:
682 frcr |= SAI_XFRCR_FSPOL; 331 frcr |= SAI_XFRCR_FSPOL;
683 break; 332 break;
684 default: 333 default:
685 dev_err(cpu_dai->dev, "Unsuppo 334 dev_err(cpu_dai->dev, "Unsupported protocol %#x\n",
686 fmt & SND_SOC_DAIFMT_F 335 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
687 return -EINVAL; 336 return -EINVAL;
688 } 337 }
689 338
690 cr1_mask |= SAI_XCR1_CKSTR; !! 339 cr1_mask |= SAI_XCR1_PRTCFG_MASK | SAI_XCR1_CKSTR;
691 frcr_mask |= SAI_XFRCR_FSPOL | SAI_XFR 340 frcr_mask |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF |
692 SAI_XFRCR_FSDEF; 341 SAI_XFRCR_FSDEF;
693 342
694 /* DAI clock strobing. Invert setting 343 /* DAI clock strobing. Invert setting previously set */
695 switch (fmt & SND_SOC_DAIFMT_INV_MASK) 344 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
696 case SND_SOC_DAIFMT_NB_NF: 345 case SND_SOC_DAIFMT_NB_NF:
697 break; 346 break;
698 case SND_SOC_DAIFMT_IB_NF: 347 case SND_SOC_DAIFMT_IB_NF:
699 cr1 ^= SAI_XCR1_CKSTR; 348 cr1 ^= SAI_XCR1_CKSTR;
700 break; 349 break;
701 case SND_SOC_DAIFMT_NB_IF: 350 case SND_SOC_DAIFMT_NB_IF:
702 frcr ^= SAI_XFRCR_FSPOL; 351 frcr ^= SAI_XFRCR_FSPOL;
703 break; 352 break;
704 case SND_SOC_DAIFMT_IB_IF: 353 case SND_SOC_DAIFMT_IB_IF:
705 /* Invert fs & sck */ 354 /* Invert fs & sck */
706 cr1 ^= SAI_XCR1_CKSTR; 355 cr1 ^= SAI_XCR1_CKSTR;
707 frcr ^= SAI_XFRCR_FSPOL; 356 frcr ^= SAI_XFRCR_FSPOL;
708 break; 357 break;
709 default: 358 default:
710 dev_err(cpu_dai->dev, "Unsuppo 359 dev_err(cpu_dai->dev, "Unsupported strobing %#x\n",
711 fmt & SND_SOC_DAIFMT_I 360 fmt & SND_SOC_DAIFMT_INV_MASK);
712 return -EINVAL; 361 return -EINVAL;
713 } 362 }
714 cr1_mask |= SAI_XCR1_CKSTR; 363 cr1_mask |= SAI_XCR1_CKSTR;
715 frcr_mask |= SAI_XFRCR_FSPOL; 364 frcr_mask |= SAI_XFRCR_FSPOL;
716 365
717 stm32_sai_sub_reg_up(sai, STM_SAI_FRCR !! 366 regmap_update_bits(sai->regmap, STM_SAI_FRCR_REGX, frcr_mask, frcr);
718 367
719 /* DAI clock master masks */ 368 /* DAI clock master masks */
720 switch (fmt & SND_SOC_DAIFMT_CLOCK_PRO !! 369 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
721 case SND_SOC_DAIFMT_BC_FC: !! 370 case SND_SOC_DAIFMT_CBM_CFM:
722 /* codec is master */ 371 /* codec is master */
723 cr1 |= SAI_XCR1_SLAVE; 372 cr1 |= SAI_XCR1_SLAVE;
724 sai->master = false; 373 sai->master = false;
725 break; 374 break;
726 case SND_SOC_DAIFMT_BP_FP: !! 375 case SND_SOC_DAIFMT_CBS_CFS:
727 sai->master = true; 376 sai->master = true;
728 break; 377 break;
729 default: 378 default:
730 dev_err(cpu_dai->dev, "Unsuppo 379 dev_err(cpu_dai->dev, "Unsupported mode %#x\n",
731 fmt & SND_SOC_DAIFMT_C !! 380 fmt & SND_SOC_DAIFMT_MASTER_MASK);
732 return -EINVAL; 381 return -EINVAL;
733 } 382 }
734 <<
735 /* Set slave mode if sub-block is sync <<
736 if (sai->sync) { <<
737 dev_dbg(cpu_dai->dev, "Synchro <<
738 cr1 |= SAI_XCR1_SLAVE; <<
739 sai->master = false; <<
740 } <<
741 <<
742 cr1_mask |= SAI_XCR1_SLAVE; 383 cr1_mask |= SAI_XCR1_SLAVE;
743 384
744 conf_update: !! 385 /* do not generate master by default */
745 ret = stm32_sai_sub_reg_up(sai, STM_SA !! 386 cr1 |= SAI_XCR1_NODIV;
>> 387 cr1_mask |= SAI_XCR1_NODIV;
>> 388
>> 389 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, cr1_mask, cr1);
746 if (ret < 0) { 390 if (ret < 0) {
747 dev_err(cpu_dai->dev, "Failed 391 dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
748 return ret; 392 return ret;
749 } 393 }
750 394
751 sai->fmt = fmt; 395 sai->fmt = fmt;
752 396
753 return 0; 397 return 0;
754 } 398 }
755 399
756 static int stm32_sai_startup(struct snd_pcm_su 400 static int stm32_sai_startup(struct snd_pcm_substream *substream,
757 struct snd_soc_da 401 struct snd_soc_dai *cpu_dai)
758 { 402 {
759 struct stm32_sai_sub_data *sai = snd_s 403 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
760 int imr, cr2, ret; 404 int imr, cr2, ret;
761 unsigned long flags; <<
762 405
763 spin_lock_irqsave(&sai->irq_lock, flag <<
764 sai->substream = substream; 406 sai->substream = substream;
765 spin_unlock_irqrestore(&sai->irq_lock, <<
766 <<
767 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { <<
768 snd_pcm_hw_constraint_mask64(s <<
769 S <<
770 S <<
771 snd_pcm_hw_constraint_single(s <<
772 S <<
773 } <<
774 407
775 ret = clk_prepare_enable(sai->sai_ck); 408 ret = clk_prepare_enable(sai->sai_ck);
776 if (ret < 0) { 409 if (ret < 0) {
777 dev_err(cpu_dai->dev, "Failed 410 dev_err(cpu_dai->dev, "Failed to enable clock: %d\n", ret);
778 return ret; 411 return ret;
779 } 412 }
780 413
781 /* Enable ITs */ 414 /* Enable ITs */
782 stm32_sai_sub_reg_wr(sai, STM_SAI_CLRF !! 415 regmap_update_bits(sai->regmap, STM_SAI_SR_REGX,
783 SAI_XCLRFR_MASK, !! 416 SAI_XSR_MASK, (unsigned int)~SAI_XSR_MASK);
>> 417
>> 418 regmap_update_bits(sai->regmap, STM_SAI_CLRFR_REGX,
>> 419 SAI_XCLRFR_MASK, SAI_XCLRFR_MASK);
784 420
785 imr = SAI_XIMR_OVRUDRIE; 421 imr = SAI_XIMR_OVRUDRIE;
786 if (STM_SAI_IS_CAPTURE(sai)) { 422 if (STM_SAI_IS_CAPTURE(sai)) {
787 stm32_sai_sub_reg_rd(sai, STM_ !! 423 regmap_read(sai->regmap, STM_SAI_CR2_REGX, &cr2);
788 if (cr2 & SAI_XCR2_MUTECNT_MAS 424 if (cr2 & SAI_XCR2_MUTECNT_MASK)
789 imr |= SAI_XIMR_MUTEDE 425 imr |= SAI_XIMR_MUTEDETIE;
790 } 426 }
791 427
792 if (sai->master) 428 if (sai->master)
793 imr |= SAI_XIMR_WCKCFGIE; 429 imr |= SAI_XIMR_WCKCFGIE;
794 else 430 else
795 imr |= SAI_XIMR_AFSDETIE | SAI 431 imr |= SAI_XIMR_AFSDETIE | SAI_XIMR_LFSDETIE;
796 432
797 stm32_sai_sub_reg_up(sai, STM_SAI_IMR_ !! 433 regmap_update_bits(sai->regmap, STM_SAI_IMR_REGX,
798 SAI_XIMR_MASK, im !! 434 SAI_XIMR_MASK, imr);
799 435
800 return 0; 436 return 0;
801 } 437 }
802 438
803 static int stm32_sai_set_config(struct snd_soc 439 static int stm32_sai_set_config(struct snd_soc_dai *cpu_dai,
804 struct snd_pcm 440 struct snd_pcm_substream *substream,
805 struct snd_pcm 441 struct snd_pcm_hw_params *params)
806 { 442 {
807 struct stm32_sai_sub_data *sai = snd_s 443 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
808 int cr1, cr1_mask, ret; 444 int cr1, cr1_mask, ret;
>> 445 int fth = STM_SAI_FIFO_TH_HALF;
809 446
810 /* !! 447 /* FIFO config */
811 * DMA bursts increment is set to 4 wo !! 448 regmap_update_bits(sai->regmap, STM_SAI_CR2_REGX,
812 * SAI fifo threshold is set to half f !! 449 SAI_XCR2_FFLUSH | SAI_XCR2_FTH_MASK,
813 * for DMA incoming bursts. !! 450 SAI_XCR2_FFLUSH | SAI_XCR2_FTH_SET(fth));
814 */ <<
815 stm32_sai_sub_reg_wr(sai, STM_SAI_CR2_ <<
816 SAI_XCR2_FFLUSH | <<
817 SAI_XCR2_FFLUSH | <<
818 SAI_XCR2_FTH_SET( <<
819 <<
820 /* DS bits in CR1 not set for SPDIF (s <<
821 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { <<
822 sai->spdif_frm_cnt = 0; <<
823 return 0; <<
824 } <<
825 451
826 /* Mode, data format and channel confi 452 /* Mode, data format and channel config */
827 cr1_mask = SAI_XCR1_DS_MASK; !! 453 cr1 = SAI_XCR1_PRTCFG_SET(SAI_FREE_PROTOCOL);
828 switch (params_format(params)) { 454 switch (params_format(params)) {
829 case SNDRV_PCM_FORMAT_S8: 455 case SNDRV_PCM_FORMAT_S8:
830 cr1 = SAI_XCR1_DS_SET(SAI_DATA !! 456 cr1 |= SAI_XCR1_DS_SET(SAI_DATASIZE_8);
831 break; 457 break;
832 case SNDRV_PCM_FORMAT_S16_LE: 458 case SNDRV_PCM_FORMAT_S16_LE:
833 cr1 = SAI_XCR1_DS_SET(SAI_DATA !! 459 cr1 |= SAI_XCR1_DS_SET(SAI_DATASIZE_16);
834 break; 460 break;
835 case SNDRV_PCM_FORMAT_S32_LE: 461 case SNDRV_PCM_FORMAT_S32_LE:
836 cr1 = SAI_XCR1_DS_SET(SAI_DATA !! 462 cr1 |= SAI_XCR1_DS_SET(SAI_DATASIZE_32);
837 break; 463 break;
838 default: 464 default:
839 dev_err(cpu_dai->dev, "Data fo !! 465 dev_err(cpu_dai->dev, "Data format not supported");
840 return -EINVAL; 466 return -EINVAL;
841 } 467 }
>> 468 cr1_mask = SAI_XCR1_DS_MASK | SAI_XCR1_PRTCFG_MASK;
>> 469
>> 470 cr1_mask |= SAI_XCR1_RX_TX;
>> 471 if (STM_SAI_IS_CAPTURE(sai))
>> 472 cr1 |= SAI_XCR1_RX_TX;
842 473
843 cr1_mask |= SAI_XCR1_MONO; 474 cr1_mask |= SAI_XCR1_MONO;
844 if ((sai->slots == 2) && (params_chann 475 if ((sai->slots == 2) && (params_channels(params) == 1))
845 cr1 |= SAI_XCR1_MONO; 476 cr1 |= SAI_XCR1_MONO;
846 477
847 ret = stm32_sai_sub_reg_up(sai, STM_SA !! 478 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, cr1_mask, cr1);
848 if (ret < 0) { 479 if (ret < 0) {
849 dev_err(cpu_dai->dev, "Failed 480 dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
850 return ret; 481 return ret;
851 } 482 }
852 483
>> 484 /* DMA config */
>> 485 sai->dma_params.maxburst = STM_SAI_FIFO_SIZE * fth / sizeof(u32);
>> 486 snd_soc_dai_set_dma_data(cpu_dai, substream, (void *)&sai->dma_params);
>> 487
853 return 0; 488 return 0;
854 } 489 }
855 490
856 static int stm32_sai_set_slots(struct snd_soc_ 491 static int stm32_sai_set_slots(struct snd_soc_dai *cpu_dai)
857 { 492 {
858 struct stm32_sai_sub_data *sai = snd_s 493 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
859 int slotr, slot_sz; 494 int slotr, slot_sz;
860 495
861 stm32_sai_sub_reg_rd(sai, STM_SAI_SLOT !! 496 regmap_read(sai->regmap, STM_SAI_SLOTR_REGX, &slotr);
862 497
863 /* 498 /*
864 * If SLOTSZ is set to auto in SLOTR, 499 * If SLOTSZ is set to auto in SLOTR, align slot width on data size
865 * By default slot width = data size, 500 * By default slot width = data size, if not forced from DT
866 */ 501 */
867 slot_sz = slotr & SAI_XSLOTR_SLOTSZ_MA 502 slot_sz = slotr & SAI_XSLOTR_SLOTSZ_MASK;
868 if (slot_sz == SAI_XSLOTR_SLOTSZ_SET(S 503 if (slot_sz == SAI_XSLOTR_SLOTSZ_SET(SAI_SLOT_SIZE_AUTO))
869 sai->slot_width = sai->data_si 504 sai->slot_width = sai->data_size;
870 505
871 if (sai->slot_width < sai->data_size) 506 if (sai->slot_width < sai->data_size) {
872 dev_err(cpu_dai->dev, 507 dev_err(cpu_dai->dev,
873 "Data size %d larger t 508 "Data size %d larger than slot width\n",
874 sai->data_size); 509 sai->data_size);
875 return -EINVAL; 510 return -EINVAL;
876 } 511 }
877 512
878 /* Slot number is set to 2, if not spe 513 /* Slot number is set to 2, if not specified in DT */
879 if (!sai->slots) 514 if (!sai->slots)
880 sai->slots = 2; 515 sai->slots = 2;
881 516
882 /* The number of slots in the audio fr 517 /* The number of slots in the audio frame is equal to NBSLOT[3:0] + 1*/
883 stm32_sai_sub_reg_up(sai, STM_SAI_SLOT !! 518 regmap_update_bits(sai->regmap, STM_SAI_SLOTR_REGX,
884 SAI_XSLOTR_NBSLOT !! 519 SAI_XSLOTR_NBSLOT_MASK,
885 SAI_XSLOTR_NBSLOT !! 520 SAI_XSLOTR_NBSLOT_SET((sai->slots - 1)));
886 521
887 /* Set default slots mask if not alrea 522 /* Set default slots mask if not already set from DT */
888 if (!(slotr & SAI_XSLOTR_SLOTEN_MASK)) 523 if (!(slotr & SAI_XSLOTR_SLOTEN_MASK)) {
889 sai->slot_mask = (1 << sai->sl 524 sai->slot_mask = (1 << sai->slots) - 1;
890 stm32_sai_sub_reg_up(sai, !! 525 regmap_update_bits(sai->regmap,
891 STM_SAI_S !! 526 STM_SAI_SLOTR_REGX, SAI_XSLOTR_SLOTEN_MASK,
892 SAI_XSLOT !! 527 SAI_XSLOTR_SLOTEN_SET(sai->slot_mask));
893 } 528 }
894 529
895 dev_dbg(cpu_dai->dev, "Slots %d, slot 530 dev_dbg(cpu_dai->dev, "Slots %d, slot width %d\n",
896 sai->slots, sai->slot_width); 531 sai->slots, sai->slot_width);
897 532
898 return 0; 533 return 0;
899 } 534 }
900 535
901 static void stm32_sai_set_frame(struct snd_soc 536 static void stm32_sai_set_frame(struct snd_soc_dai *cpu_dai)
902 { 537 {
903 struct stm32_sai_sub_data *sai = snd_s 538 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
904 int fs_active, offset, format; 539 int fs_active, offset, format;
905 int frcr, frcr_mask; 540 int frcr, frcr_mask;
906 541
907 format = sai->fmt & SND_SOC_DAIFMT_FOR 542 format = sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
908 sai->fs_length = sai->slot_width * sai 543 sai->fs_length = sai->slot_width * sai->slots;
909 544
910 fs_active = sai->fs_length / 2; 545 fs_active = sai->fs_length / 2;
911 if ((format == SND_SOC_DAIFMT_DSP_A) | 546 if ((format == SND_SOC_DAIFMT_DSP_A) ||
912 (format == SND_SOC_DAIFMT_DSP_B)) 547 (format == SND_SOC_DAIFMT_DSP_B))
913 fs_active = 1; 548 fs_active = 1;
914 549
915 frcr = SAI_XFRCR_FRL_SET((sai->fs_leng 550 frcr = SAI_XFRCR_FRL_SET((sai->fs_length - 1));
916 frcr |= SAI_XFRCR_FSALL_SET((fs_active 551 frcr |= SAI_XFRCR_FSALL_SET((fs_active - 1));
917 frcr_mask = SAI_XFRCR_FRL_MASK | SAI_X 552 frcr_mask = SAI_XFRCR_FRL_MASK | SAI_XFRCR_FSALL_MASK;
918 553
919 dev_dbg(cpu_dai->dev, "Frame length %d 554 dev_dbg(cpu_dai->dev, "Frame length %d, frame active %d\n",
920 sai->fs_length, fs_active); 555 sai->fs_length, fs_active);
921 556
922 stm32_sai_sub_reg_up(sai, STM_SAI_FRCR !! 557 regmap_update_bits(sai->regmap, STM_SAI_FRCR_REGX, frcr_mask, frcr);
923 558
924 if ((sai->fmt & SND_SOC_DAIFMT_FORMAT_ 559 if ((sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_LSB) {
925 offset = sai->slot_width - sai 560 offset = sai->slot_width - sai->data_size;
926 561
927 stm32_sai_sub_reg_up(sai, STM_ !! 562 regmap_update_bits(sai->regmap, STM_SAI_SLOTR_REGX,
928 SAI_XSLOT !! 563 SAI_XSLOTR_FBOFF_MASK,
929 SAI_XSLOT !! 564 SAI_XSLOTR_FBOFF_SET(offset));
930 } <<
931 } <<
932 <<
933 static void stm32_sai_init_iec958_status(struc <<
934 { <<
935 unsigned char *cs = sai->iec958.status <<
936 <<
937 cs[0] = IEC958_AES0_CON_NOT_COPYRIGHT <<
938 cs[1] = IEC958_AES1_CON_GENERAL; <<
939 cs[2] = IEC958_AES2_CON_SOURCE_UNSPEC <<
940 cs[3] = IEC958_AES3_CON_CLOCK_1000PPM <<
941 } <<
942 <<
943 static void stm32_sai_set_iec958_status(struct <<
944 struct <<
945 { <<
946 if (!runtime) <<
947 return; <<
948 <<
949 /* Force the sample rate according to <<
950 mutex_lock(&sai->ctrl_lock); <<
951 switch (runtime->rate) { <<
952 case 22050: <<
953 sai->iec958.status[3] = IEC958 <<
954 break; <<
955 case 44100: <<
956 sai->iec958.status[3] = IEC958 <<
957 break; <<
958 case 88200: <<
959 sai->iec958.status[3] = IEC958 <<
960 break; <<
961 case 176400: <<
962 sai->iec958.status[3] = IEC958 <<
963 break; <<
964 case 24000: <<
965 sai->iec958.status[3] = IEC958 <<
966 break; <<
967 case 48000: <<
968 sai->iec958.status[3] = IEC958 <<
969 break; <<
970 case 96000: <<
971 sai->iec958.status[3] = IEC958 <<
972 break; <<
973 case 192000: <<
974 sai->iec958.status[3] = IEC958 <<
975 break; <<
976 case 32000: <<
977 sai->iec958.status[3] = IEC958 <<
978 break; <<
979 default: <<
980 sai->iec958.status[3] = IEC958 <<
981 break; <<
982 } 565 }
983 mutex_unlock(&sai->ctrl_lock); <<
984 } 566 }
985 567
986 static int stm32_sai_configure_clock(struct sn 568 static int stm32_sai_configure_clock(struct snd_soc_dai *cpu_dai,
987 struct sn 569 struct snd_pcm_hw_params *params)
988 { 570 {
989 struct stm32_sai_sub_data *sai = snd_s 571 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
990 int div = 0, cr1 = 0; !! 572 int cr1, mask, div = 0;
991 int sai_clk_rate, mclk_ratio, den; !! 573 int sai_clk_rate, mclk_ratio, den, ret;
992 unsigned int rate = params_rate(params !! 574 int version = sai->pdata->conf->version;
993 int ret; <<
994 575
995 if (!sai->sai_mclk) { !! 576 if (!sai->mclk_rate) {
996 ret = stm32_sai_set_parent_clo !! 577 dev_err(cpu_dai->dev, "Mclk rate is null\n");
997 if (ret) !! 578 return -EINVAL;
998 return ret; <<
999 } 579 }
>> 580
>> 581 if (!(params_rate(params) % 11025))
>> 582 clk_set_parent(sai->sai_ck, sai->pdata->clk_x11k);
>> 583 else
>> 584 clk_set_parent(sai->sai_ck, sai->pdata->clk_x8k);
1000 sai_clk_rate = clk_get_rate(sai->sai_ 585 sai_clk_rate = clk_get_rate(sai->sai_ck);
1001 586
1002 if (STM_SAI_IS_F4(sai->pdata)) { 587 if (STM_SAI_IS_F4(sai->pdata)) {
1003 /* mclk on (NODIV=0) !! 588 /*
1004 * mclk_rate = 256 * fs !! 589 * mclk_rate = 256 * fs
1005 * MCKDIV = 0 if sai_ck < 3 !! 590 * MCKDIV = 0 if sai_ck < 3/2 * mclk_rate
1006 * MCKDIV = sai_ck / (2 * m !! 591 * MCKDIV = sai_ck / (2 * mclk_rate) otherwise
1007 * mclk off (NODIV=1) <<
1008 * MCKDIV ignored. sck = sa <<
1009 */ 592 */
1010 if (!sai->mclk_rate) !! 593 if (2 * sai_clk_rate >= 3 * sai->mclk_rate)
1011 return 0; !! 594 div = DIV_ROUND_CLOSEST(sai_clk_rate,
1012 !! 595 2 * sai->mclk_rate);
1013 if (2 * sai_clk_rate >= 3 * s <<
1014 div = stm32_sai_get_c <<
1015 <<
1016 if (div < 0) <<
1017 return div; <<
1018 } <<
1019 } else { 596 } else {
1020 /* 597 /*
1021 * TDM mode : 598 * TDM mode :
1022 * mclk on 599 * mclk on
1023 * MCKDIV = sai_ck / (ws 600 * MCKDIV = sai_ck / (ws x 256) (NOMCK=0. OSR=0)
1024 * MCKDIV = sai_ck / (ws 601 * MCKDIV = sai_ck / (ws x 512) (NOMCK=0. OSR=1)
1025 * mclk off 602 * mclk off
1026 * MCKDIV = sai_ck / (fr 603 * MCKDIV = sai_ck / (frl x ws) (NOMCK=1)
1027 * Note: NOMCK/NODIV correspo 604 * Note: NOMCK/NODIV correspond to same bit.
1028 */ 605 */
1029 if (STM_SAI_PROTOCOL_IS_SPDIF !! 606 if (sai->mclk_rate) {
1030 div = stm32_sai_get_c !! 607 mclk_ratio = sai->mclk_rate / params_rate(params);
1031 !! 608 if (mclk_ratio != 256) {
1032 if (div < 0) <<
1033 return div; <<
1034 } else { <<
1035 if (sai->mclk_rate) { <<
1036 mclk_ratio = <<
1037 if (mclk_rati 609 if (mclk_ratio == 512) {
>> 610 mask = SAI_XCR1_OSR;
1038 cr1 = 611 cr1 = SAI_XCR1_OSR;
1039 } else if (mc !! 612 } else {
1040 dev_e 613 dev_err(cpu_dai->dev,
1041 614 "Wrong mclk ratio %d\n",
1042 615 mclk_ratio);
1043 retur 616 return -EINVAL;
1044 } 617 }
1045 <<
1046 stm32_sai_sub <<
1047 <<
1048 <<
1049 <<
1050 div = stm32_s <<
1051 <<
1052 if (div < 0) <<
1053 retur <<
1054 } else { <<
1055 /* mclk-fs no <<
1056 den = sai->fs <<
1057 div = stm32_s <<
1058 <<
1059 if (div < 0) <<
1060 retur <<
1061 } 618 }
>> 619 div = DIV_ROUND_CLOSEST(sai_clk_rate, sai->mclk_rate);
>> 620 } else {
>> 621 /* mclk-fs not set, master clock not active. NOMCK=1 */
>> 622 den = sai->fs_length * params_rate(params);
>> 623 div = DIV_ROUND_CLOSEST(sai_clk_rate, den);
1062 } 624 }
1063 } 625 }
1064 626
1065 return stm32_sai_set_clk_div(sai, div !! 627 if (div > SAI_XCR1_MCKDIV_MAX(version)) {
>> 628 dev_err(cpu_dai->dev, "Divider %d out of range\n", div);
>> 629 return -EINVAL;
>> 630 }
>> 631 dev_dbg(cpu_dai->dev, "SAI clock %d, divider %d\n", sai_clk_rate, div);
>> 632
>> 633 mask = SAI_XCR1_MCKDIV_MASK(SAI_XCR1_MCKDIV_WIDTH(version));
>> 634 cr1 = SAI_XCR1_MCKDIV_SET(div);
>> 635 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, mask, cr1);
>> 636 if (ret < 0) {
>> 637 dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
>> 638 return ret;
>> 639 }
>> 640
>> 641 return 0;
1066 } 642 }
1067 643
1068 static int stm32_sai_hw_params(struct snd_pcm 644 static int stm32_sai_hw_params(struct snd_pcm_substream *substream,
1069 struct snd_pcm 645 struct snd_pcm_hw_params *params,
1070 struct snd_soc 646 struct snd_soc_dai *cpu_dai)
1071 { 647 {
1072 struct stm32_sai_sub_data *sai = snd_ 648 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
1073 int ret; 649 int ret;
1074 650
1075 sai->data_size = params_width(params) 651 sai->data_size = params_width(params);
1076 652
1077 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { !! 653 ret = stm32_sai_set_slots(cpu_dai);
1078 /* Rate not already set in ru !! 654 if (ret < 0)
1079 substream->runtime->rate = pa !! 655 return ret;
1080 stm32_sai_set_iec958_status(s !! 656 stm32_sai_set_frame(cpu_dai);
1081 } else { <<
1082 ret = stm32_sai_set_slots(cpu <<
1083 if (ret < 0) <<
1084 return ret; <<
1085 stm32_sai_set_frame(cpu_dai); <<
1086 } <<
1087 657
1088 ret = stm32_sai_set_config(cpu_dai, s 658 ret = stm32_sai_set_config(cpu_dai, substream, params);
1089 if (ret) 659 if (ret)
1090 return ret; 660 return ret;
1091 661
1092 if (sai->master) 662 if (sai->master)
1093 ret = stm32_sai_configure_clo 663 ret = stm32_sai_configure_clock(cpu_dai, params);
1094 664
1095 return ret; 665 return ret;
1096 } 666 }
1097 667
1098 static int stm32_sai_trigger(struct snd_pcm_s 668 static int stm32_sai_trigger(struct snd_pcm_substream *substream, int cmd,
1099 struct snd_soc_d 669 struct snd_soc_dai *cpu_dai)
1100 { 670 {
1101 struct stm32_sai_sub_data *sai = snd_ 671 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
1102 int ret; 672 int ret;
1103 673
1104 switch (cmd) { 674 switch (cmd) {
1105 case SNDRV_PCM_TRIGGER_START: 675 case SNDRV_PCM_TRIGGER_START:
1106 case SNDRV_PCM_TRIGGER_RESUME: 676 case SNDRV_PCM_TRIGGER_RESUME:
1107 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 677 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1108 dev_dbg(cpu_dai->dev, "Enable 678 dev_dbg(cpu_dai->dev, "Enable DMA and SAI\n");
1109 679
1110 stm32_sai_sub_reg_up(sai, STM !! 680 regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX,
1111 SAI_XCR1 !! 681 SAI_XCR1_DMAEN, SAI_XCR1_DMAEN);
1112 682
1113 /* Enable SAI */ 683 /* Enable SAI */
1114 ret = stm32_sai_sub_reg_up(sa !! 684 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX,
1115 SA !! 685 SAI_XCR1_SAIEN, SAI_XCR1_SAIEN);
1116 if (ret < 0) 686 if (ret < 0)
1117 dev_err(cpu_dai->dev, 687 dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
1118 break; 688 break;
1119 case SNDRV_PCM_TRIGGER_SUSPEND: 689 case SNDRV_PCM_TRIGGER_SUSPEND:
1120 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 690 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1121 case SNDRV_PCM_TRIGGER_STOP: 691 case SNDRV_PCM_TRIGGER_STOP:
1122 dev_dbg(cpu_dai->dev, "Disabl 692 dev_dbg(cpu_dai->dev, "Disable DMA and SAI\n");
1123 693
1124 stm32_sai_sub_reg_up(sai, STM !! 694 regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX,
1125 SAI_XIMR !! 695 SAI_XCR1_SAIEN,
1126 !! 696 (unsigned int)~SAI_XCR1_SAIEN);
1127 stm32_sai_sub_reg_up(sai, STM !! 697
1128 SAI_XCR1 !! 698 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX,
1129 (unsigne !! 699 SAI_XCR1_DMAEN,
1130 !! 700 (unsigned int)~SAI_XCR1_DMAEN);
1131 ret = stm32_sai_sub_reg_up(sa <<
1132 SA <<
1133 (u <<
1134 if (ret < 0) 701 if (ret < 0)
1135 dev_err(cpu_dai->dev, 702 dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
1136 <<
1137 if (STM_SAI_PROTOCOL_IS_SPDIF <<
1138 sai->spdif_frm_cnt = <<
1139 break; 703 break;
1140 default: 704 default:
1141 return -EINVAL; 705 return -EINVAL;
1142 } 706 }
1143 707
1144 return ret; 708 return ret;
1145 } 709 }
1146 710
1147 static void stm32_sai_shutdown(struct snd_pcm 711 static void stm32_sai_shutdown(struct snd_pcm_substream *substream,
1148 struct snd_soc 712 struct snd_soc_dai *cpu_dai)
1149 { 713 {
1150 struct stm32_sai_sub_data *sai = snd_ 714 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
1151 unsigned long flags; <<
1152 715
1153 stm32_sai_sub_reg_up(sai, STM_SAI_IMR !! 716 regmap_update_bits(sai->regmap, STM_SAI_IMR_REGX, SAI_XIMR_MASK, 0);
1154 717
1155 clk_disable_unprepare(sai->sai_ck); !! 718 regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, SAI_XCR1_NODIV,
>> 719 SAI_XCR1_NODIV);
1156 720
1157 spin_lock_irqsave(&sai->irq_lock, fla !! 721 clk_disable_unprepare(sai->sai_ck);
1158 sai->substream = NULL; 722 sai->substream = NULL;
1159 spin_unlock_irqrestore(&sai->irq_lock <<
1160 } <<
1161 <<
1162 static int stm32_sai_pcm_new(struct snd_soc_p <<
1163 struct snd_soc_d <<
1164 { <<
1165 struct stm32_sai_sub_data *sai = dev_ <<
1166 struct snd_kcontrol_new knew = iec958 <<
1167 <<
1168 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { <<
1169 dev_dbg(&sai->pdev->dev, "%s: <<
1170 knew.device = rtd->pcm->devic <<
1171 return snd_ctl_add(rtd->pcm-> <<
1172 } <<
1173 <<
1174 return 0; <<
1175 } 723 }
1176 724
1177 static int stm32_sai_dai_probe(struct snd_soc 725 static int stm32_sai_dai_probe(struct snd_soc_dai *cpu_dai)
1178 { 726 {
1179 struct stm32_sai_sub_data *sai = dev_ 727 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev);
1180 int cr1 = 0, cr1_mask, ret; <<
1181 <<
1182 sai->cpu_dai = cpu_dai; <<
1183 728
1184 sai->dma_params.addr = (dma_addr_t)(s 729 sai->dma_params.addr = (dma_addr_t)(sai->phys_addr + STM_SAI_DR_REGX);
1185 /* !! 730 sai->dma_params.maxburst = 1;
1186 * DMA supports 4, 8 or 16 burst size <<
1187 * as it allows bytes, half-word and <<
1188 * constraints). <<
1189 */ <<
1190 sai->dma_params.maxburst = 4; <<
1191 if (sai->pdata->conf.fifo_size < 8) <<
1192 sai->dma_params.maxburst = 1; <<
1193 /* Buswidth will be set by framework 731 /* Buswidth will be set by framework at runtime */
1194 sai->dma_params.addr_width = DMA_SLAV 732 sai->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
1195 733
1196 if (STM_SAI_IS_PLAYBACK(sai)) 734 if (STM_SAI_IS_PLAYBACK(sai))
1197 snd_soc_dai_init_dma_data(cpu 735 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params, NULL);
1198 else 736 else
1199 snd_soc_dai_init_dma_data(cpu 737 snd_soc_dai_init_dma_data(cpu_dai, NULL, &sai->dma_params);
1200 738
1201 /* Next settings are not relevant for !! 739 return 0;
1202 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) <<
1203 return 0; <<
1204 <<
1205 cr1_mask = SAI_XCR1_RX_TX; <<
1206 if (STM_SAI_IS_CAPTURE(sai)) <<
1207 cr1 |= SAI_XCR1_RX_TX; <<
1208 <<
1209 /* Configure synchronization */ <<
1210 if (sai->sync == SAI_SYNC_EXTERNAL) { <<
1211 /* Configure synchro client a <<
1212 ret = sai->pdata->set_sync(sa <<
1213 sa <<
1214 if (ret) <<
1215 return ret; <<
1216 } <<
1217 <<
1218 cr1_mask |= SAI_XCR1_SYNCEN_MASK; <<
1219 cr1 |= SAI_XCR1_SYNCEN_SET(sai->sync) <<
1220 <<
1221 return stm32_sai_sub_reg_up(sai, STM_ <<
1222 } 740 }
1223 741
1224 static const struct snd_soc_dai_ops stm32_sai 742 static const struct snd_soc_dai_ops stm32_sai_pcm_dai_ops = {
1225 .probe = stm32_sai_dai_probe <<
1226 .set_sysclk = stm32_sai_set_syscl 743 .set_sysclk = stm32_sai_set_sysclk,
1227 .set_fmt = stm32_sai_set_dai_f 744 .set_fmt = stm32_sai_set_dai_fmt,
1228 .set_tdm_slot = stm32_sai_set_dai_t 745 .set_tdm_slot = stm32_sai_set_dai_tdm_slot,
1229 .startup = stm32_sai_startup, 746 .startup = stm32_sai_startup,
1230 .hw_params = stm32_sai_hw_params 747 .hw_params = stm32_sai_hw_params,
1231 .trigger = stm32_sai_trigger, 748 .trigger = stm32_sai_trigger,
1232 .shutdown = stm32_sai_shutdown, 749 .shutdown = stm32_sai_shutdown,
1233 .pcm_new = stm32_sai_pcm_new, <<
1234 }; <<
1235 <<
1236 static const struct snd_soc_dai_ops stm32_sai <<
1237 .probe = stm32_sai_dai_probe <<
1238 .set_sysclk = stm32_sai_set_syscl <<
1239 .set_fmt = stm32_sai_set_dai_f <<
1240 .set_tdm_slot = stm32_sai_set_dai_t <<
1241 .startup = stm32_sai_startup, <<
1242 .hw_params = stm32_sai_hw_params <<
1243 .trigger = stm32_sai_trigger, <<
1244 .shutdown = stm32_sai_shutdown, <<
1245 }; <<
1246 <<
1247 static int stm32_sai_pcm_process_spdif(struct <<
1248 int ch <<
1249 unsign <<
1250 { <<
1251 struct snd_pcm_runtime *runtime = sub <<
1252 struct snd_soc_pcm_runtime *rtd = snd <<
1253 struct snd_soc_dai *cpu_dai = snd_soc <<
1254 struct stm32_sai_sub_data *sai = dev_ <<
1255 int *ptr = (int *)(runtime->dma_area <<
1256 channel * (runtime <<
1257 ssize_t cnt = bytes_to_samples(runtim <<
1258 unsigned int frm_cnt = sai->spdif_frm <<
1259 unsigned int byte; <<
1260 unsigned int mask; <<
1261 <<
1262 do { <<
1263 *ptr = ((*ptr >> 8) & 0x00fff <<
1264 <<
1265 /* Set channel status bit */ <<
1266 byte = frm_cnt >> 3; <<
1267 mask = 1 << (frm_cnt - (byte <<
1268 if (sai->iec958.status[byte] <<
1269 *ptr |= 0x04000000; <<
1270 ptr++; <<
1271 <<
1272 if (!(cnt % 2)) <<
1273 frm_cnt++; <<
1274 <<
1275 if (frm_cnt == SAI_IEC60958_B <<
1276 frm_cnt = 0; <<
1277 } while (--cnt); <<
1278 sai->spdif_frm_cnt = frm_cnt; <<
1279 <<
1280 return 0; <<
1281 } <<
1282 <<
1283 /* No support of mmap in S/PDIF mode */ <<
1284 static const struct snd_pcm_hardware stm32_sa <<
1285 .info = SNDRV_PCM_INFO_INTERLEAVED, <<
1286 .buffer_bytes_max = 8 * PAGE_SIZE, <<
1287 .period_bytes_min = 1024, <<
1288 .period_bytes_max = PAGE_SIZE, <<
1289 .periods_min = 2, <<
1290 .periods_max = 8, <<
1291 }; 750 };
1292 751
1293 static const struct snd_pcm_hardware stm32_sa 752 static const struct snd_pcm_hardware stm32_sai_pcm_hw = {
1294 .info = SNDRV_PCM_INFO_INTERLEAVED | 753 .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP,
1295 .buffer_bytes_max = 8 * PAGE_SIZE, 754 .buffer_bytes_max = 8 * PAGE_SIZE,
1296 .period_bytes_min = 1024, /* 5ms at 4 755 .period_bytes_min = 1024, /* 5ms at 48kHz */
1297 .period_bytes_max = PAGE_SIZE, 756 .period_bytes_max = PAGE_SIZE,
1298 .periods_min = 2, 757 .periods_min = 2,
1299 .periods_max = 8, 758 .periods_max = 8,
1300 }; 759 };
1301 760
1302 static struct snd_soc_dai_driver stm32_sai_pl !! 761 static struct snd_soc_dai_driver stm32_sai_playback_dai[] = {
>> 762 {
>> 763 .probe = stm32_sai_dai_probe,
1303 .id = 1, /* avoid call to fmt 764 .id = 1, /* avoid call to fmt_single_name() */
1304 .playback = { 765 .playback = {
1305 .channels_min = 1, 766 .channels_min = 1,
1306 .channels_max = 16, !! 767 .channels_max = 2,
1307 .rate_min = 8000, 768 .rate_min = 8000,
1308 .rate_max = 192000, 769 .rate_max = 192000,
1309 .rates = SNDRV_PCM_RA 770 .rates = SNDRV_PCM_RATE_CONTINUOUS,
1310 /* DMA does not suppo 771 /* DMA does not support 24 bits transfers */
1311 .formats = 772 .formats =
1312 SNDRV_PCM_FMT 773 SNDRV_PCM_FMTBIT_S8 |
1313 SNDRV_PCM_FMT 774 SNDRV_PCM_FMTBIT_S16_LE |
1314 SNDRV_PCM_FMT 775 SNDRV_PCM_FMTBIT_S32_LE,
1315 }, 776 },
1316 .ops = &stm32_sai_pcm_dai_ops 777 .ops = &stm32_sai_pcm_dai_ops,
>> 778 }
1317 }; 779 };
1318 780
1319 static struct snd_soc_dai_driver stm32_sai_ca !! 781 static struct snd_soc_dai_driver stm32_sai_capture_dai[] = {
>> 782 {
>> 783 .probe = stm32_sai_dai_probe,
1320 .id = 1, /* avoid call to fmt 784 .id = 1, /* avoid call to fmt_single_name() */
1321 .capture = { 785 .capture = {
1322 .channels_min = 1, 786 .channels_min = 1,
1323 .channels_max = 16, !! 787 .channels_max = 2,
1324 .rate_min = 8000, 788 .rate_min = 8000,
1325 .rate_max = 192000, 789 .rate_max = 192000,
1326 .rates = SNDRV_PCM_RA 790 .rates = SNDRV_PCM_RATE_CONTINUOUS,
1327 /* DMA does not suppo 791 /* DMA does not support 24 bits transfers */
1328 .formats = 792 .formats =
1329 SNDRV_PCM_FMT 793 SNDRV_PCM_FMTBIT_S8 |
1330 SNDRV_PCM_FMT 794 SNDRV_PCM_FMTBIT_S16_LE |
1331 SNDRV_PCM_FMT 795 SNDRV_PCM_FMTBIT_S32_LE,
1332 }, 796 },
1333 .ops = &stm32_sai_pcm_dai_ops !! 797 .ops = &stm32_sai_pcm_dai_ops,
>> 798 }
1334 }; 799 };
1335 800
1336 static const struct snd_dmaengine_pcm_config 801 static const struct snd_dmaengine_pcm_config stm32_sai_pcm_config = {
1337 .pcm_hardware = &stm32_sai_pcm_hw, !! 802 .pcm_hardware = &stm32_sai_pcm_hw,
1338 .prepare_slave_config = snd_dmaengine !! 803 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1339 }; <<
1340 <<
1341 static const struct snd_dmaengine_pcm_config <<
1342 .pcm_hardware = &stm32_sai_pcm_hw_spd <<
1343 .prepare_slave_config = snd_dmaengine <<
1344 .process = stm32_sai_pcm_process_spdi <<
1345 }; 804 };
1346 805
1347 static const struct snd_soc_component_driver 806 static const struct snd_soc_component_driver stm32_component = {
1348 .name = "stm32-sai", 807 .name = "stm32-sai",
1349 .legacy_dai_naming = 1, <<
1350 }; 808 };
1351 809
1352 static const struct of_device_id stm32_sai_su 810 static const struct of_device_id stm32_sai_sub_ids[] = {
1353 { .compatible = "st,stm32-sai-sub-a", 811 { .compatible = "st,stm32-sai-sub-a",
1354 .data = (void *)STM_SAI_A_ID}, 812 .data = (void *)STM_SAI_A_ID},
1355 { .compatible = "st,stm32-sai-sub-b", 813 { .compatible = "st,stm32-sai-sub-b",
1356 .data = (void *)STM_SAI_B_ID}, 814 .data = (void *)STM_SAI_B_ID},
1357 {} 815 {}
1358 }; 816 };
1359 MODULE_DEVICE_TABLE(of, stm32_sai_sub_ids); 817 MODULE_DEVICE_TABLE(of, stm32_sai_sub_ids);
1360 818
1361 static int stm32_sai_sub_parse_of(struct plat 819 static int stm32_sai_sub_parse_of(struct platform_device *pdev,
1362 struct stm3 820 struct stm32_sai_sub_data *sai)
1363 { 821 {
1364 struct device_node *np = pdev->dev.of 822 struct device_node *np = pdev->dev.of_node;
1365 struct resource *res; 823 struct resource *res;
1366 void __iomem *base; 824 void __iomem *base;
1367 struct of_phandle_args args; <<
1368 int ret; <<
1369 825
1370 if (!np) 826 if (!np)
1371 return -ENODEV; 827 return -ENODEV;
1372 828
1373 base = devm_platform_get_and_ioremap_ !! 829 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> 830 base = devm_ioremap_resource(&pdev->dev, res);
1374 if (IS_ERR(base)) 831 if (IS_ERR(base))
1375 return PTR_ERR(base); 832 return PTR_ERR(base);
1376 833
1377 sai->phys_addr = res->start; 834 sai->phys_addr = res->start;
1378 835
1379 sai->regmap_config = &stm32_sai_sub_r 836 sai->regmap_config = &stm32_sai_sub_regmap_config_f4;
1380 /* Note: PDM registers not available !! 837 /* Note: PDM registers not available for H7 sub-block B */
1381 if (STM_SAI_HAS_PDM(sai) && STM_SAI_I !! 838 if (STM_SAI_IS_H7(sai->pdata) && STM_SAI_IS_SUB_A(sai))
1382 sai->regmap_config = &stm32_s 839 sai->regmap_config = &stm32_sai_sub_regmap_config_h7;
1383 840
1384 /* !! 841 sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "sai_ck",
1385 * Do not manage peripheral clock thr !! 842 base, sai->regmap_config);
1386 * can lead to circular locking issue !! 843 if (IS_ERR(sai->regmap)) {
1387 * Manage peripheral clock directly i !! 844 dev_err(&pdev->dev, "Failed to initialize MMIO\n");
1388 */ !! 845 return PTR_ERR(sai->regmap);
1389 sai->regmap = devm_regmap_init_mmio(& !! 846 }
1390 s <<
1391 if (IS_ERR(sai->regmap)) <<
1392 return dev_err_probe(&pdev->d <<
1393 "Regmap <<
1394 847
1395 /* Get direction property */ 848 /* Get direction property */
1396 if (of_property_match_string(np, "dma 849 if (of_property_match_string(np, "dma-names", "tx") >= 0) {
1397 sai->dir = SNDRV_PCM_STREAM_P 850 sai->dir = SNDRV_PCM_STREAM_PLAYBACK;
1398 } else if (of_property_match_string(n 851 } else if (of_property_match_string(np, "dma-names", "rx") >= 0) {
1399 sai->dir = SNDRV_PCM_STREAM_C 852 sai->dir = SNDRV_PCM_STREAM_CAPTURE;
1400 } else { 853 } else {
1401 dev_err(&pdev->dev, "Unsuppor 854 dev_err(&pdev->dev, "Unsupported direction\n");
1402 return -EINVAL; 855 return -EINVAL;
1403 } 856 }
1404 857
1405 /* Get spdif iec60958 property */ <<
1406 sai->spdif = false; <<
1407 if (of_property_present(np, "st,iec60 <<
1408 if (!STM_SAI_HAS_SPDIF(sai) | <<
1409 sai->dir == SNDRV_PCM_STR <<
1410 dev_err(&pdev->dev, " <<
1411 return -EINVAL; <<
1412 } <<
1413 stm32_sai_init_iec958_status( <<
1414 sai->spdif = true; <<
1415 sai->master = true; <<
1416 } <<
1417 <<
1418 /* Get synchronization property */ <<
1419 args.np = NULL; <<
1420 ret = of_parse_phandle_with_fixed_arg <<
1421 if (ret < 0 && ret != -ENOENT) { <<
1422 dev_err(&pdev->dev, "Failed t <<
1423 return ret; <<
1424 } <<
1425 <<
1426 sai->sync = SAI_SYNC_NONE; <<
1427 if (args.np) { <<
1428 if (args.np == np) { <<
1429 dev_err(&pdev->dev, " <<
1430 of_node_put(args.np); <<
1431 return -EINVAL; <<
1432 } <<
1433 <<
1434 sai->np_sync_provider = of_g <<
1435 if (!sai->np_sync_provider) { <<
1436 dev_err(&pdev->dev, " <<
1437 np); <<
1438 of_node_put(args.np); <<
1439 return -ENODEV; <<
1440 } <<
1441 <<
1442 sai->sync = SAI_SYNC_INTERNAL <<
1443 if (sai->np_sync_provider != <<
1444 if (!STM_SAI_HAS_EXT_ <<
1445 dev_err(&pdev <<
1446 "Exte <<
1447 of_node_put(a <<
1448 return -EINVA <<
1449 } <<
1450 sai->sync = SAI_SYNC_ <<
1451 <<
1452 sai->synci = args.arg <<
1453 if (sai->synci < 1 || <<
1454 (sai->synci > (SA <<
1455 dev_err(&pdev <<
1456 of_node_put(a <<
1457 return -EINVA <<
1458 } <<
1459 <<
1460 if (of_property_match <<
1461 <<
1462 sai->synco = <<
1463 <<
1464 if (of_property_match <<
1465 <<
1466 sai->synco = <<
1467 <<
1468 if (!sai->synco) { <<
1469 dev_err(&pdev <<
1470 of_node_put(a <<
1471 return -EINVA <<
1472 } <<
1473 } <<
1474 <<
1475 dev_dbg(&pdev->dev, "%s synch <<
1476 pdev->name, args.np-> <<
1477 } <<
1478 <<
1479 of_node_put(args.np); <<
1480 sai->sai_ck = devm_clk_get(&pdev->dev 858 sai->sai_ck = devm_clk_get(&pdev->dev, "sai_ck");
1481 if (IS_ERR(sai->sai_ck)) !! 859 if (IS_ERR(sai->sai_ck)) {
1482 return dev_err_probe(&pdev->d !! 860 dev_err(&pdev->dev, "Missing kernel clock sai_ck\n");
1483 "Missing !! 861 return PTR_ERR(sai->sai_ck);
>> 862 }
1484 863
1485 ret = clk_prepare(sai->pdata->pclk); !! 864 return 0;
1486 if (ret < 0) !! 865 }
1487 return ret; <<
1488 866
1489 if (STM_SAI_IS_F4(sai->pdata)) !! 867 static int stm32_sai_sub_dais_init(struct platform_device *pdev,
1490 return 0; !! 868 struct stm32_sai_sub_data *sai)
>> 869 {
>> 870 sai->cpu_dai_drv = devm_kzalloc(&pdev->dev,
>> 871 sizeof(struct snd_soc_dai_driver),
>> 872 GFP_KERNEL);
>> 873 if (!sai->cpu_dai_drv)
>> 874 return -ENOMEM;
1491 875
1492 /* Register mclk provider if requeste !! 876 sai->cpu_dai_drv->name = dev_name(&pdev->dev);
1493 if (of_property_present(np, "#clock-c !! 877 if (STM_SAI_IS_PLAYBACK(sai)) {
1494 ret = stm32_sai_add_mclk_prov !! 878 memcpy(sai->cpu_dai_drv, &stm32_sai_playback_dai,
1495 if (ret < 0) !! 879 sizeof(stm32_sai_playback_dai));
1496 return ret; !! 880 sai->cpu_dai_drv->playback.stream_name = sai->cpu_dai_drv->name;
1497 } else { 881 } else {
1498 sai->sai_mclk = devm_clk_get_ !! 882 memcpy(sai->cpu_dai_drv, &stm32_sai_capture_dai,
1499 if (IS_ERR(sai->sai_mclk)) !! 883 sizeof(stm32_sai_capture_dai));
1500 return PTR_ERR(sai->s !! 884 sai->cpu_dai_drv->capture.stream_name = sai->cpu_dai_drv->name;
1501 } 885 }
1502 886
1503 return 0; 887 return 0;
1504 } 888 }
1505 889
1506 static int stm32_sai_sub_probe(struct platfor 890 static int stm32_sai_sub_probe(struct platform_device *pdev)
1507 { 891 {
1508 struct stm32_sai_sub_data *sai; 892 struct stm32_sai_sub_data *sai;
1509 const struct snd_dmaengine_pcm_config !! 893 const struct of_device_id *of_id;
1510 int ret; 894 int ret;
1511 895
1512 sai = devm_kzalloc(&pdev->dev, sizeof 896 sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
1513 if (!sai) 897 if (!sai)
1514 return -ENOMEM; 898 return -ENOMEM;
1515 899
1516 sai->id = (uintptr_t)device_get_match !! 900 of_id = of_match_device(stm32_sai_sub_ids, &pdev->dev);
>> 901 if (!of_id)
>> 902 return -EINVAL;
>> 903 sai->id = (uintptr_t)of_id->data;
1517 904
1518 sai->pdev = pdev; 905 sai->pdev = pdev;
1519 mutex_init(&sai->ctrl_lock); <<
1520 spin_lock_init(&sai->irq_lock); <<
1521 platform_set_drvdata(pdev, sai); 906 platform_set_drvdata(pdev, sai);
1522 907
1523 sai->pdata = dev_get_drvdata(pdev->de 908 sai->pdata = dev_get_drvdata(pdev->dev.parent);
1524 if (!sai->pdata) { 909 if (!sai->pdata) {
1525 dev_err(&pdev->dev, "Parent d 910 dev_err(&pdev->dev, "Parent device data not available\n");
1526 return -EINVAL; 911 return -EINVAL;
1527 } 912 }
1528 913
1529 ret = stm32_sai_sub_parse_of(pdev, sa 914 ret = stm32_sai_sub_parse_of(pdev, sai);
1530 if (ret) 915 if (ret)
1531 return ret; 916 return ret;
1532 917
1533 if (STM_SAI_IS_PLAYBACK(sai)) !! 918 ret = stm32_sai_sub_dais_init(pdev, sai);
1534 sai->cpu_dai_drv = stm32_sai_ !! 919 if (ret)
1535 else !! 920 return ret;
1536 sai->cpu_dai_drv = stm32_sai_ <<
1537 sai->cpu_dai_drv.name = dev_name(&pde <<
1538 921
1539 ret = devm_request_irq(&pdev->dev, sa 922 ret = devm_request_irq(&pdev->dev, sai->pdata->irq, stm32_sai_isr,
1540 IRQF_SHARED, d 923 IRQF_SHARED, dev_name(&pdev->dev), sai);
1541 if (ret) { 924 if (ret) {
1542 dev_err(&pdev->dev, "IRQ requ 925 dev_err(&pdev->dev, "IRQ request returned %d\n", ret);
1543 return ret; 926 return ret;
1544 } 927 }
1545 928
1546 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) !! 929 ret = devm_snd_soc_register_component(&pdev->dev, &stm32_component,
1547 conf = &stm32_sai_pcm_config_ !! 930 sai->cpu_dai_drv, 1);
1548 <<
1549 ret = snd_dmaengine_pcm_register(&pde <<
1550 if (ret) 931 if (ret)
1551 return dev_err_probe(&pdev->d !! 932 return ret;
1552 933
1553 ret = snd_soc_register_component(&pde !! 934 ret = devm_snd_dmaengine_pcm_register(&pdev->dev,
1554 &sai !! 935 &stm32_sai_pcm_config, 0);
1555 if (ret) { 936 if (ret) {
1556 snd_dmaengine_pcm_unregister( !! 937 dev_err(&pdev->dev, "Could not register pcm dma\n");
1557 return ret; 938 return ret;
1558 } 939 }
1559 940
1560 pm_runtime_enable(&pdev->dev); <<
1561 <<
1562 return 0; 941 return 0;
1563 } 942 }
1564 943
1565 static void stm32_sai_sub_remove(struct platf <<
1566 { <<
1567 struct stm32_sai_sub_data *sai = dev_ <<
1568 <<
1569 clk_unprepare(sai->pdata->pclk); <<
1570 snd_dmaengine_pcm_unregister(&pdev->d <<
1571 snd_soc_unregister_component(&pdev->d <<
1572 pm_runtime_disable(&pdev->dev); <<
1573 } <<
1574 <<
1575 #ifdef CONFIG_PM_SLEEP <<
1576 static int stm32_sai_sub_suspend(struct devic <<
1577 { <<
1578 struct stm32_sai_sub_data *sai = dev_ <<
1579 int ret; <<
1580 <<
1581 ret = clk_enable(sai->pdata->pclk); <<
1582 if (ret < 0) <<
1583 return ret; <<
1584 <<
1585 regcache_cache_only(sai->regmap, true <<
1586 regcache_mark_dirty(sai->regmap); <<
1587 <<
1588 clk_disable(sai->pdata->pclk); <<
1589 <<
1590 return 0; <<
1591 } <<
1592 <<
1593 static int stm32_sai_sub_resume(struct device <<
1594 { <<
1595 struct stm32_sai_sub_data *sai = dev_ <<
1596 int ret; <<
1597 <<
1598 ret = clk_enable(sai->pdata->pclk); <<
1599 if (ret < 0) <<
1600 return ret; <<
1601 <<
1602 regcache_cache_only(sai->regmap, fals <<
1603 ret = regcache_sync(sai->regmap); <<
1604 <<
1605 clk_disable(sai->pdata->pclk); <<
1606 <<
1607 return ret; <<
1608 } <<
1609 #endif /* CONFIG_PM_SLEEP */ <<
1610 <<
1611 static const struct dev_pm_ops stm32_sai_sub_ <<
1612 SET_SYSTEM_SLEEP_PM_OPS(stm32_sai_sub <<
1613 }; <<
1614 <<
1615 static struct platform_driver stm32_sai_sub_d 944 static struct platform_driver stm32_sai_sub_driver = {
1616 .driver = { 945 .driver = {
1617 .name = "st,stm32-sai-sub", 946 .name = "st,stm32-sai-sub",
1618 .of_match_table = stm32_sai_s 947 .of_match_table = stm32_sai_sub_ids,
1619 .pm = &stm32_sai_sub_pm_ops, <<
1620 }, 948 },
1621 .probe = stm32_sai_sub_probe, 949 .probe = stm32_sai_sub_probe,
1622 .remove = stm32_sai_sub_remove, <<
1623 }; 950 };
1624 951
1625 module_platform_driver(stm32_sai_sub_driver); 952 module_platform_driver(stm32_sai_sub_driver);
1626 953
1627 MODULE_DESCRIPTION("STM32 Soc SAI sub-block I 954 MODULE_DESCRIPTION("STM32 Soc SAI sub-block Interface");
1628 MODULE_AUTHOR("Olivier Moysan <olivier.moysan 955 MODULE_AUTHOR("Olivier Moysan <olivier.moysan@st.com>");
1629 MODULE_ALIAS("platform:st,stm32-sai-sub"); 956 MODULE_ALIAS("platform:st,stm32-sai-sub");
1630 MODULE_LICENSE("GPL v2"); 957 MODULE_LICENSE("GPL v2");
1631 958
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