1 /* SPDX-License-Identifier: GPL-2.0-only */ 1
2 /*
3 * tegra210_amx.h - Definitions for Tegra210 A
4 *
5 * Copyright (c) 2021, NVIDIA CORPORATION. Al
6 *
7 */
8
9 #ifndef __TEGRA210_AMX_H__
10 #define __TEGRA210_AMX_H__
11
12 /* Register offsets from TEGRA210_AMX*_BASE */
13 #define TEGRA210_AMX_RX_STATUS
14 #define TEGRA210_AMX_RX_INT_STATUS
15 #define TEGRA210_AMX_RX_INT_MASK
16 #define TEGRA210_AMX_RX_INT_SET
17 #define TEGRA210_AMX_RX_INT_CLEAR
18 #define TEGRA210_AMX_RX1_CIF_CTRL
19 #define TEGRA210_AMX_RX2_CIF_CTRL
20 #define TEGRA210_AMX_RX3_CIF_CTRL
21 #define TEGRA210_AMX_RX4_CIF_CTRL
22 #define TEGRA210_AMX_TX_STATUS
23 #define TEGRA210_AMX_TX_INT_STATUS
24 #define TEGRA210_AMX_TX_INT_MASK
25 #define TEGRA210_AMX_TX_INT_SET
26 #define TEGRA210_AMX_TX_INT_CLEAR
27 #define TEGRA210_AMX_TX_CIF_CTRL
28 #define TEGRA210_AMX_ENABLE
29 #define TEGRA210_AMX_SOFT_RESET
30 #define TEGRA210_AMX_CG
31 #define TEGRA210_AMX_STATUS
32 #define TEGRA210_AMX_INT_STATUS
33 #define TEGRA210_AMX_CTRL
34 #define TEGRA210_AMX_OUT_BYTE_EN0
35 #define TEGRA210_AMX_OUT_BYTE_EN1
36 #define TEGRA210_AMX_CYA
37 #define TEGRA210_AMX_CFG_RAM_CTRL
38 #define TEGRA210_AMX_CFG_RAM_DATA
39
40 #define TEGRA194_AMX_RX1_FRAME_PERIOD
41 #define TEGRA194_AMX_RX4_FRAME_PERIOD
42 #define TEGRA194_AMX_RX4_LAST_FRAME_PERIOD
43
44 /* Fields in TEGRA210_AMX_ENABLE */
45 #define TEGRA210_AMX_ENABLE_SHIFT
46
47 /* Fields in TEGRA210_AMX_CTRL */
48 #define TEGRA210_AMX_CTRL_MSTR_RX_NUM_SHIFT
49 #define TEGRA210_AMX_CTRL_MSTR_RX_NUM_MASK
50
51 #define TEGRA210_AMX_CTRL_RX_DEP_SHIFT
52 #define TEGRA210_AMX_CTRL_RX_DEP_MASK
53
54 /* Fields in TEGRA210_AMX_CFG_RAM_CTRL */
55 #define TEGRA210_AMX_CFG_RAM_CTRL_RW_SHIFT
56 #define TEGRA210_AMX_CFG_RAM_CTRL_RW_WRITE
57
58 #define TEGRA210_AMX_CFG_RAM_CTRL_ADDR_INIT_EN
59 #define TEGRA210_AMX_CFG_RAM_CTRL_ADDR_INIT_EN
60
61 #define TEGRA210_AMX_CFG_RAM_CTRL_SEQ_ACCESS_E
62 #define TEGRA210_AMX_CFG_RAM_CTRL_SEQ_ACCESS_E
63
64 #define TEGRA210_AMX_CFG_CTRL_RAM_ADDR_SHIFT
65
66 /* Fields in TEGRA210_AMX_SOFT_RESET */
67 #define TEGRA210_AMX_SOFT_RESET_SOFT_EN
68 #define TEGRA210_AMX_SOFT_RESET_SOFT_RESET_MAS
69
70 #define TEGRA210_AMX_AUDIOCIF_CH_STRIDE
71 #define TEGRA210_AMX_RAM_DEPTH
72 #define TEGRA210_AMX_MAP_STREAM_NUM_SHIFT
73 #define TEGRA210_AMX_MAP_WORD_NUM_SHIFT
74 #define TEGRA210_AMX_MAP_BYTE_NUM_SHIFT
75
76 enum {
77 TEGRA210_AMX_WAIT_ON_ALL,
78 TEGRA210_AMX_WAIT_ON_ANY,
79 };
80
81 struct tegra210_amx_soc_data {
82 const struct regmap_config *regmap_con
83 bool auto_disable;
84 };
85
86 struct tegra210_amx {
87 const struct tegra210_amx_soc_data *so
88 unsigned int map[TEGRA210_AMX_RAM_DEPT
89 struct regmap *regmap;
90 unsigned int byte_mask[2];
91 };
92
93 #endif
94
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