1 /* SPDX-License-Identifier: GPL-2.0-only */ 1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* 2 /*
3 * tegra210_amx.h - Definitions for Tegra210 A 3 * tegra210_amx.h - Definitions for Tegra210 AMX driver
4 * 4 *
5 * Copyright (c) 2021, NVIDIA CORPORATION. Al 5 * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
6 * 6 *
7 */ 7 */
8 8
9 #ifndef __TEGRA210_AMX_H__ 9 #ifndef __TEGRA210_AMX_H__
10 #define __TEGRA210_AMX_H__ 10 #define __TEGRA210_AMX_H__
11 11
12 /* Register offsets from TEGRA210_AMX*_BASE */ 12 /* Register offsets from TEGRA210_AMX*_BASE */
13 #define TEGRA210_AMX_RX_STATUS 13 #define TEGRA210_AMX_RX_STATUS 0x0c
14 #define TEGRA210_AMX_RX_INT_STATUS 14 #define TEGRA210_AMX_RX_INT_STATUS 0x10
15 #define TEGRA210_AMX_RX_INT_MASK 15 #define TEGRA210_AMX_RX_INT_MASK 0x14
16 #define TEGRA210_AMX_RX_INT_SET 16 #define TEGRA210_AMX_RX_INT_SET 0x18
17 #define TEGRA210_AMX_RX_INT_CLEAR 17 #define TEGRA210_AMX_RX_INT_CLEAR 0x1c
18 #define TEGRA210_AMX_RX1_CIF_CTRL 18 #define TEGRA210_AMX_RX1_CIF_CTRL 0x20
19 #define TEGRA210_AMX_RX2_CIF_CTRL 19 #define TEGRA210_AMX_RX2_CIF_CTRL 0x24
20 #define TEGRA210_AMX_RX3_CIF_CTRL 20 #define TEGRA210_AMX_RX3_CIF_CTRL 0x28
21 #define TEGRA210_AMX_RX4_CIF_CTRL 21 #define TEGRA210_AMX_RX4_CIF_CTRL 0x2c
22 #define TEGRA210_AMX_TX_STATUS 22 #define TEGRA210_AMX_TX_STATUS 0x4c
23 #define TEGRA210_AMX_TX_INT_STATUS 23 #define TEGRA210_AMX_TX_INT_STATUS 0x50
24 #define TEGRA210_AMX_TX_INT_MASK 24 #define TEGRA210_AMX_TX_INT_MASK 0x54
25 #define TEGRA210_AMX_TX_INT_SET 25 #define TEGRA210_AMX_TX_INT_SET 0x58
26 #define TEGRA210_AMX_TX_INT_CLEAR 26 #define TEGRA210_AMX_TX_INT_CLEAR 0x5c
27 #define TEGRA210_AMX_TX_CIF_CTRL 27 #define TEGRA210_AMX_TX_CIF_CTRL 0x60
28 #define TEGRA210_AMX_ENABLE 28 #define TEGRA210_AMX_ENABLE 0x80
29 #define TEGRA210_AMX_SOFT_RESET 29 #define TEGRA210_AMX_SOFT_RESET 0x84
30 #define TEGRA210_AMX_CG 30 #define TEGRA210_AMX_CG 0x88
31 #define TEGRA210_AMX_STATUS 31 #define TEGRA210_AMX_STATUS 0x8c
32 #define TEGRA210_AMX_INT_STATUS 32 #define TEGRA210_AMX_INT_STATUS 0x90
33 #define TEGRA210_AMX_CTRL 33 #define TEGRA210_AMX_CTRL 0xa4
34 #define TEGRA210_AMX_OUT_BYTE_EN0 34 #define TEGRA210_AMX_OUT_BYTE_EN0 0xa8
35 #define TEGRA210_AMX_OUT_BYTE_EN1 35 #define TEGRA210_AMX_OUT_BYTE_EN1 0xac
36 #define TEGRA210_AMX_CYA 36 #define TEGRA210_AMX_CYA 0xb0
37 #define TEGRA210_AMX_CFG_RAM_CTRL 37 #define TEGRA210_AMX_CFG_RAM_CTRL 0xb8
38 #define TEGRA210_AMX_CFG_RAM_DATA 38 #define TEGRA210_AMX_CFG_RAM_DATA 0xbc
39 39
40 #define TEGRA194_AMX_RX1_FRAME_PERIOD 40 #define TEGRA194_AMX_RX1_FRAME_PERIOD 0xc0
41 #define TEGRA194_AMX_RX4_FRAME_PERIOD 41 #define TEGRA194_AMX_RX4_FRAME_PERIOD 0xcc
42 #define TEGRA194_AMX_RX4_LAST_FRAME_PERIOD 42 #define TEGRA194_AMX_RX4_LAST_FRAME_PERIOD 0xdc
43 43
44 /* Fields in TEGRA210_AMX_ENABLE */ 44 /* Fields in TEGRA210_AMX_ENABLE */
45 #define TEGRA210_AMX_ENABLE_SHIFT 45 #define TEGRA210_AMX_ENABLE_SHIFT 0
46 46
47 /* Fields in TEGRA210_AMX_CTRL */ 47 /* Fields in TEGRA210_AMX_CTRL */
48 #define TEGRA210_AMX_CTRL_MSTR_RX_NUM_SHIFT 48 #define TEGRA210_AMX_CTRL_MSTR_RX_NUM_SHIFT 14
49 #define TEGRA210_AMX_CTRL_MSTR_RX_NUM_MASK 49 #define TEGRA210_AMX_CTRL_MSTR_RX_NUM_MASK (3 << TEGRA210_AMX_CTRL_MSTR_RX_NUM_SHIFT)
50 50
51 #define TEGRA210_AMX_CTRL_RX_DEP_SHIFT 51 #define TEGRA210_AMX_CTRL_RX_DEP_SHIFT 12
52 #define TEGRA210_AMX_CTRL_RX_DEP_MASK 52 #define TEGRA210_AMX_CTRL_RX_DEP_MASK (3 << TEGRA210_AMX_CTRL_RX_DEP_SHIFT)
53 53
54 /* Fields in TEGRA210_AMX_CFG_RAM_CTRL */ 54 /* Fields in TEGRA210_AMX_CFG_RAM_CTRL */
55 #define TEGRA210_AMX_CFG_RAM_CTRL_RW_SHIFT 55 #define TEGRA210_AMX_CFG_RAM_CTRL_RW_SHIFT 14
56 #define TEGRA210_AMX_CFG_RAM_CTRL_RW_WRITE 56 #define TEGRA210_AMX_CFG_RAM_CTRL_RW_WRITE (1 << TEGRA210_AMX_CFG_RAM_CTRL_RW_SHIFT)
57 57
58 #define TEGRA210_AMX_CFG_RAM_CTRL_ADDR_INIT_EN 58 #define TEGRA210_AMX_CFG_RAM_CTRL_ADDR_INIT_EN_SHIFT 13
59 #define TEGRA210_AMX_CFG_RAM_CTRL_ADDR_INIT_EN 59 #define TEGRA210_AMX_CFG_RAM_CTRL_ADDR_INIT_EN (1 << TEGRA210_AMX_CFG_RAM_CTRL_ADDR_INIT_EN_SHIFT)
60 60
61 #define TEGRA210_AMX_CFG_RAM_CTRL_SEQ_ACCESS_E 61 #define TEGRA210_AMX_CFG_RAM_CTRL_SEQ_ACCESS_EN_SHIFT 12
62 #define TEGRA210_AMX_CFG_RAM_CTRL_SEQ_ACCESS_E 62 #define TEGRA210_AMX_CFG_RAM_CTRL_SEQ_ACCESS_EN (1 << TEGRA210_AMX_CFG_RAM_CTRL_SEQ_ACCESS_EN_SHIFT)
63 63
64 #define TEGRA210_AMX_CFG_CTRL_RAM_ADDR_SHIFT 64 #define TEGRA210_AMX_CFG_CTRL_RAM_ADDR_SHIFT 0
65 65
66 /* Fields in TEGRA210_AMX_SOFT_RESET */ 66 /* Fields in TEGRA210_AMX_SOFT_RESET */
67 #define TEGRA210_AMX_SOFT_RESET_SOFT_EN 67 #define TEGRA210_AMX_SOFT_RESET_SOFT_EN 1
68 #define TEGRA210_AMX_SOFT_RESET_SOFT_RESET_MAS 68 #define TEGRA210_AMX_SOFT_RESET_SOFT_RESET_MASK TEGRA210_AMX_SOFT_RESET_SOFT_EN
69 69
70 #define TEGRA210_AMX_AUDIOCIF_CH_STRIDE 70 #define TEGRA210_AMX_AUDIOCIF_CH_STRIDE 4
71 #define TEGRA210_AMX_RAM_DEPTH 71 #define TEGRA210_AMX_RAM_DEPTH 16
72 #define TEGRA210_AMX_MAP_STREAM_NUM_SHIFT 72 #define TEGRA210_AMX_MAP_STREAM_NUM_SHIFT 6
73 #define TEGRA210_AMX_MAP_WORD_NUM_SHIFT 73 #define TEGRA210_AMX_MAP_WORD_NUM_SHIFT 2
74 #define TEGRA210_AMX_MAP_BYTE_NUM_SHIFT 74 #define TEGRA210_AMX_MAP_BYTE_NUM_SHIFT 0
75 75
76 enum { 76 enum {
77 TEGRA210_AMX_WAIT_ON_ALL, 77 TEGRA210_AMX_WAIT_ON_ALL,
78 TEGRA210_AMX_WAIT_ON_ANY, 78 TEGRA210_AMX_WAIT_ON_ANY,
79 }; 79 };
80 80
81 struct tegra210_amx_soc_data { 81 struct tegra210_amx_soc_data {
82 const struct regmap_config *regmap_con 82 const struct regmap_config *regmap_conf;
83 bool auto_disable; 83 bool auto_disable;
84 }; 84 };
85 85
86 struct tegra210_amx { 86 struct tegra210_amx {
87 const struct tegra210_amx_soc_data *so 87 const struct tegra210_amx_soc_data *soc_data;
88 unsigned int map[TEGRA210_AMX_RAM_DEPT 88 unsigned int map[TEGRA210_AMX_RAM_DEPTH];
89 struct regmap *regmap; 89 struct regmap *regmap;
90 unsigned int byte_mask[2]; 90 unsigned int byte_mask[2];
91 }; 91 };
92 92
93 #endif 93 #endif
94 94
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