1 /* SPDX-License-Identifier: GPL-2.0-or-later * <<
2 /* 1 /*
3 * Driver for the AT73C213 16-bit stereo DAC o 2 * Driver for the AT73C213 16-bit stereo DAC on Atmel ATSTK1000
4 * 3 *
5 * Copyright (C) 2006 - 2007 Atmel Corporation 4 * Copyright (C) 2006 - 2007 Atmel Corporation
>> 5 *
>> 6 * This program is free software; you can redistribute it and/or
>> 7 * modify it under the terms of the GNU General Public License as
>> 8 * published by the Free Software Foundation; either version 2 of the
>> 9 * License, or (at your option) any later version.
>> 10 *
>> 11 * This program is distributed in the hope that it will be useful, but
>> 12 * WITHOUT ANY WARRANTY; without even the implied warranty of
>> 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
>> 14 * General Public License for more details.
>> 15 *
>> 16 * You should have received a copy of the GNU General Public License
>> 17 * along with this program; if not, write to the Free Software
>> 18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
>> 19 * 02111-1307, USA.
>> 20 *
>> 21 * The full GNU General Public License is included in this
>> 22 * distribution in the file called COPYING.
6 */ 23 */
7 24
8 #ifndef _SND_AT73C213_H 25 #ifndef _SND_AT73C213_H
9 #define _SND_AT73C213_H 26 #define _SND_AT73C213_H
10 27
11 /* DAC control register */ 28 /* DAC control register */
12 #define DAC_CTRL 0x00 29 #define DAC_CTRL 0x00
13 #define DAC_CTRL_ONPADRV 7 30 #define DAC_CTRL_ONPADRV 7
14 #define DAC_CTRL_ONAUXIN 6 31 #define DAC_CTRL_ONAUXIN 6
15 #define DAC_CTRL_ONDACR 5 32 #define DAC_CTRL_ONDACR 5
16 #define DAC_CTRL_ONDACL 4 33 #define DAC_CTRL_ONDACL 4
17 #define DAC_CTRL_ONLNOR 3 34 #define DAC_CTRL_ONLNOR 3
18 #define DAC_CTRL_ONLNOL 2 35 #define DAC_CTRL_ONLNOL 2
19 #define DAC_CTRL_ONLNIR 1 36 #define DAC_CTRL_ONLNIR 1
20 #define DAC_CTRL_ONLNIL 0 37 #define DAC_CTRL_ONLNIL 0
21 38
22 /* DAC left line in gain register */ 39 /* DAC left line in gain register */
23 #define DAC_LLIG 0x01 40 #define DAC_LLIG 0x01
24 #define DAC_LLIG_LLIG 0 41 #define DAC_LLIG_LLIG 0
25 42
26 /* DAC right line in gain register */ 43 /* DAC right line in gain register */
27 #define DAC_RLIG 0x02 44 #define DAC_RLIG 0x02
28 #define DAC_RLIG_RLIG 0 45 #define DAC_RLIG_RLIG 0
29 46
30 /* DAC Left Master Playback Gain Register */ 47 /* DAC Left Master Playback Gain Register */
31 #define DAC_LMPG 0x03 48 #define DAC_LMPG 0x03
32 #define DAC_LMPG_LMPG 0 49 #define DAC_LMPG_LMPG 0
33 50
34 /* DAC Right Master Playback Gain Register */ 51 /* DAC Right Master Playback Gain Register */
35 #define DAC_RMPG 0x04 52 #define DAC_RMPG 0x04
36 #define DAC_RMPG_RMPG 0 53 #define DAC_RMPG_RMPG 0
37 54
38 /* DAC Left Line Out Gain Register */ 55 /* DAC Left Line Out Gain Register */
39 #define DAC_LLOG 0x05 56 #define DAC_LLOG 0x05
40 #define DAC_LLOG_LLOG 0 57 #define DAC_LLOG_LLOG 0
41 58
42 /* DAC Right Line Out Gain Register */ 59 /* DAC Right Line Out Gain Register */
43 #define DAC_RLOG 0x06 60 #define DAC_RLOG 0x06
44 #define DAC_RLOG_RLOG 0 61 #define DAC_RLOG_RLOG 0
45 62
46 /* DAC Output Level Control Register */ 63 /* DAC Output Level Control Register */
47 #define DAC_OLC 0x07 64 #define DAC_OLC 0x07
48 #define DAC_OLC_RSHORT 7 65 #define DAC_OLC_RSHORT 7
49 #define DAC_OLC_ROLC 4 66 #define DAC_OLC_ROLC 4
50 #define DAC_OLC_LSHORT 3 67 #define DAC_OLC_LSHORT 3
51 #define DAC_OLC_LOLC 0 68 #define DAC_OLC_LOLC 0
52 69
53 /* DAC Mixer Control Register */ 70 /* DAC Mixer Control Register */
54 #define DAC_MC 0x08 71 #define DAC_MC 0x08
55 #define DAC_MC_INVR 5 72 #define DAC_MC_INVR 5
56 #define DAC_MC_INVL 4 73 #define DAC_MC_INVL 4
57 #define DAC_MC_RMSMIN2 3 74 #define DAC_MC_RMSMIN2 3
58 #define DAC_MC_RMSMIN1 2 75 #define DAC_MC_RMSMIN1 2
59 #define DAC_MC_LMSMIN2 1 76 #define DAC_MC_LMSMIN2 1
60 #define DAC_MC_LMSMIN1 0 77 #define DAC_MC_LMSMIN1 0
61 78
62 /* DAC Clock and Sampling Frequency Control Re 79 /* DAC Clock and Sampling Frequency Control Register */
63 #define DAC_CSFC 0x09 80 #define DAC_CSFC 0x09
64 #define DAC_CSFC_OVRSEL 4 81 #define DAC_CSFC_OVRSEL 4
65 82
66 /* DAC Miscellaneous Register */ 83 /* DAC Miscellaneous Register */
67 #define DAC_MISC 0x0A 84 #define DAC_MISC 0x0A
68 #define DAC_MISC_VCMCAPSEL 7 85 #define DAC_MISC_VCMCAPSEL 7
69 #define DAC_MISC_DINTSEL 4 86 #define DAC_MISC_DINTSEL 4
70 #define DAC_MISC_DITHEN 3 87 #define DAC_MISC_DITHEN 3
71 #define DAC_MISC_DEEMPEN 2 88 #define DAC_MISC_DEEMPEN 2
72 #define DAC_MISC_NBITS 0 89 #define DAC_MISC_NBITS 0
73 90
74 /* DAC Precharge Control Register */ 91 /* DAC Precharge Control Register */
75 #define DAC_PRECH 0x0C 92 #define DAC_PRECH 0x0C
76 #define DAC_PRECH_PRCHGPDRV 7 93 #define DAC_PRECH_PRCHGPDRV 7
77 #define DAC_PRECH_PRCHGAUX1 6 94 #define DAC_PRECH_PRCHGAUX1 6
78 #define DAC_PRECH_PRCHGLNOR 5 95 #define DAC_PRECH_PRCHGLNOR 5
79 #define DAC_PRECH_PRCHGLNOL 4 96 #define DAC_PRECH_PRCHGLNOL 4
80 #define DAC_PRECH_PRCHGLNIR 3 97 #define DAC_PRECH_PRCHGLNIR 3
81 #define DAC_PRECH_PRCHGLNIL 2 98 #define DAC_PRECH_PRCHGLNIL 2
82 #define DAC_PRECH_PRCHG 1 99 #define DAC_PRECH_PRCHG 1
83 #define DAC_PRECH_ONMSTR 0 100 #define DAC_PRECH_ONMSTR 0
84 101
85 /* DAC Auxiliary Input Gain Control Register * 102 /* DAC Auxiliary Input Gain Control Register */
86 #define DAC_AUXG 0x0D 103 #define DAC_AUXG 0x0D
87 #define DAC_AUXG_AUXG 0 104 #define DAC_AUXG_AUXG 0
88 105
89 /* DAC Reset Register */ 106 /* DAC Reset Register */
90 #define DAC_RST 0x10 107 #define DAC_RST 0x10
91 #define DAC_RST_RESMASK 2 108 #define DAC_RST_RESMASK 2
92 #define DAC_RST_RESFILZ 1 109 #define DAC_RST_RESFILZ 1
93 #define DAC_RST_RSTZ 0 110 #define DAC_RST_RSTZ 0
94 111
95 /* Power Amplifier Control Register */ 112 /* Power Amplifier Control Register */
96 #define PA_CTRL 0x11 113 #define PA_CTRL 0x11
97 #define PA_CTRL_APAON 6 114 #define PA_CTRL_APAON 6
98 #define PA_CTRL_APAPRECH 5 115 #define PA_CTRL_APAPRECH 5
99 #define PA_CTRL_APALP 4 116 #define PA_CTRL_APALP 4
100 #define PA_CTRL_APAGAIN 0 117 #define PA_CTRL_APAGAIN 0
101 118
102 #endif /* _SND_AT73C213_H */ 119 #endif /* _SND_AT73C213_H */
103 120
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