1 Explanation of the Linux-Kernel Memory Consist 1 Explanation of the Linux-Kernel Memory Consistency Model
2 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
3 3
4 :Author: Alan Stern <stern@rowland.harvard.edu> 4 :Author: Alan Stern <stern@rowland.harvard.edu>
5 :Created: October 2017 5 :Created: October 2017
6 6
7 .. Contents 7 .. Contents
8 8
9 1. INTRODUCTION 9 1. INTRODUCTION
10 2. BACKGROUND 10 2. BACKGROUND
11 3. A SIMPLE EXAMPLE 11 3. A SIMPLE EXAMPLE
12 4. A SELECTION OF MEMORY MODELS 12 4. A SELECTION OF MEMORY MODELS
13 5. ORDERING AND CYCLES 13 5. ORDERING AND CYCLES
14 6. EVENTS 14 6. EVENTS
15 7. THE PROGRAM ORDER RELATION: po AND po-loc 15 7. THE PROGRAM ORDER RELATION: po AND po-loc
16 8. A WARNING 16 8. A WARNING
17 9. DEPENDENCY RELATIONS: data, addr, and ctr 17 9. DEPENDENCY RELATIONS: data, addr, and ctrl
18 10. THE READS-FROM RELATION: rf, rfi, and rf 18 10. THE READS-FROM RELATION: rf, rfi, and rfe
19 11. CACHE COHERENCE AND THE COHERENCE ORDER 19 11. CACHE COHERENCE AND THE COHERENCE ORDER RELATION: co, coi, and coe
20 12. THE FROM-READS RELATION: fr, fri, and fr 20 12. THE FROM-READS RELATION: fr, fri, and fre
21 13. AN OPERATIONAL MODEL 21 13. AN OPERATIONAL MODEL
22 14. PROPAGATION ORDER RELATION: cumul-fence 22 14. PROPAGATION ORDER RELATION: cumul-fence
23 15. DERIVATION OF THE LKMM FROM THE OPERATIO 23 15. DERIVATION OF THE LKMM FROM THE OPERATIONAL MODEL
24 16. SEQUENTIAL CONSISTENCY PER VARIABLE 24 16. SEQUENTIAL CONSISTENCY PER VARIABLE
25 17. ATOMIC UPDATES: rmw 25 17. ATOMIC UPDATES: rmw
26 18. THE PRESERVED PROGRAM ORDER RELATION: pp 26 18. THE PRESERVED PROGRAM ORDER RELATION: ppo
27 19. AND THEN THERE WAS ALPHA 27 19. AND THEN THERE WAS ALPHA
28 20. THE HAPPENS-BEFORE RELATION: hb 28 20. THE HAPPENS-BEFORE RELATION: hb
29 21. THE PROPAGATES-BEFORE RELATION: pb 29 21. THE PROPAGATES-BEFORE RELATION: pb
30 22. RCU RELATIONS: rcu-link, rcu-gp, rcu-rsc !! 30 22. RCU RELATIONS: rcu-link, gp, rscs, rcu-fence, and rb
31 23. SRCU READ-SIDE CRITICAL SECTIONS !! 31 23. LOCKING
32 24. LOCKING !! 32 24. ODDS AND ENDS
33 25. PLAIN ACCESSES AND DATA RACES <<
34 26. ODDS AND ENDS <<
35 33
36 34
37 35
38 INTRODUCTION 36 INTRODUCTION
39 ------------ 37 ------------
40 38
41 The Linux-kernel memory consistency model (LKM 39 The Linux-kernel memory consistency model (LKMM) is rather complex and
42 obscure. This is particularly evident if you 40 obscure. This is particularly evident if you read through the
43 linux-kernel.bell and linux-kernel.cat files t 41 linux-kernel.bell and linux-kernel.cat files that make up the formal
44 version of the model; they are extremely terse 42 version of the model; they are extremely terse and their meanings are
45 far from clear. 43 far from clear.
46 44
47 This document describes the ideas underlying t 45 This document describes the ideas underlying the LKMM. It is meant
48 for people who want to understand how the mode 46 for people who want to understand how the model was designed. It does
49 not go into the details of the code in the .be 47 not go into the details of the code in the .bell and .cat files;
50 rather, it explains in English what the code e 48 rather, it explains in English what the code expresses symbolically.
51 49
52 Sections 2 (BACKGROUND) through 5 (ORDERING AN 50 Sections 2 (BACKGROUND) through 5 (ORDERING AND CYCLES) are aimed
53 toward beginners; they explain what memory con 51 toward beginners; they explain what memory consistency models are and
54 the basic notions shared by all such models. 52 the basic notions shared by all such models. People already familiar
55 with these concepts can skim or skip over them 53 with these concepts can skim or skip over them. Sections 6 (EVENTS)
56 through 12 (THE FROM_READS RELATION) describe 54 through 12 (THE FROM_READS RELATION) describe the fundamental
57 relations used in many models. Starting in Se 55 relations used in many models. Starting in Section 13 (AN OPERATIONAL
58 MODEL), the workings of the LKMM itself are co 56 MODEL), the workings of the LKMM itself are covered.
59 57
60 Warning: The code examples in this document ar 58 Warning: The code examples in this document are not written in the
61 proper format for litmus tests. They don't in 59 proper format for litmus tests. They don't include a header line, the
62 initializations are not enclosed in braces, th 60 initializations are not enclosed in braces, the global variables are
63 not passed by pointers, and they don't have an 61 not passed by pointers, and they don't have an "exists" clause at the
64 end. Converting them to the right format is l 62 end. Converting them to the right format is left as an exercise for
65 the reader. 63 the reader.
66 64
67 65
68 BACKGROUND 66 BACKGROUND
69 ---------- 67 ----------
70 68
71 A memory consistency model (or just memory mod 69 A memory consistency model (or just memory model, for short) is
72 something which predicts, given a piece of com 70 something which predicts, given a piece of computer code running on a
73 particular kind of system, what values may be 71 particular kind of system, what values may be obtained by the code's
74 load instructions. The LKMM makes these predi 72 load instructions. The LKMM makes these predictions for code running
75 as part of the Linux kernel. 73 as part of the Linux kernel.
76 74
77 In practice, people tend to use memory models 75 In practice, people tend to use memory models the other way around.
78 That is, given a piece of code and a collectio 76 That is, given a piece of code and a collection of values specified
79 for the loads, the model will predict whether 77 for the loads, the model will predict whether it is possible for the
80 code to run in such a way that the loads will 78 code to run in such a way that the loads will indeed obtain the
81 specified values. Of course, this is just ano 79 specified values. Of course, this is just another way of expressing
82 the same idea. 80 the same idea.
83 81
84 For code running on a uniprocessor system, the 82 For code running on a uniprocessor system, the predictions are easy:
85 Each load instruction must obtain the value wr 83 Each load instruction must obtain the value written by the most recent
86 store instruction accessing the same location 84 store instruction accessing the same location (we ignore complicating
87 factors such as DMA and mixed-size accesses.) 85 factors such as DMA and mixed-size accesses.) But on multiprocessor
88 systems, with multiple CPUs making concurrent 86 systems, with multiple CPUs making concurrent accesses to shared
89 memory locations, things aren't so simple. 87 memory locations, things aren't so simple.
90 88
91 Different architectures have differing memory 89 Different architectures have differing memory models, and the Linux
92 kernel supports a variety of architectures. T 90 kernel supports a variety of architectures. The LKMM has to be fairly
93 permissive, in the sense that any behavior all 91 permissive, in the sense that any behavior allowed by one of these
94 architectures also has to be allowed by the LK 92 architectures also has to be allowed by the LKMM.
95 93
96 94
97 A SIMPLE EXAMPLE 95 A SIMPLE EXAMPLE
98 ---------------- 96 ----------------
99 97
100 Here is a simple example to illustrate the bas 98 Here is a simple example to illustrate the basic concepts. Consider
101 some code running as part of a device driver f 99 some code running as part of a device driver for an input device. The
102 driver might contain an interrupt handler whic 100 driver might contain an interrupt handler which collects data from the
103 device, stores it in a buffer, and sets a flag 101 device, stores it in a buffer, and sets a flag to indicate the buffer
104 is full. Running concurrently on a different 102 is full. Running concurrently on a different CPU might be a part of
105 the driver code being executed by a process in 103 the driver code being executed by a process in the midst of a read(2)
106 system call. This code tests the flag to see 104 system call. This code tests the flag to see whether the buffer is
107 ready, and if it is, copies the data back to u 105 ready, and if it is, copies the data back to userspace. The buffer
108 and the flag are memory locations shared betwe 106 and the flag are memory locations shared between the two CPUs.
109 107
110 We can abstract out the important pieces of th 108 We can abstract out the important pieces of the driver code as follows
111 (the reason for using WRITE_ONCE() and READ_ON 109 (the reason for using WRITE_ONCE() and READ_ONCE() instead of simple
112 assignment statements is discussed later): 110 assignment statements is discussed later):
113 111
114 int buf = 0, flag = 0; 112 int buf = 0, flag = 0;
115 113
116 P0() 114 P0()
117 { 115 {
118 WRITE_ONCE(buf, 1); 116 WRITE_ONCE(buf, 1);
119 WRITE_ONCE(flag, 1); 117 WRITE_ONCE(flag, 1);
120 } 118 }
121 119
122 P1() 120 P1()
123 { 121 {
124 int r1; 122 int r1;
125 int r2 = 0; 123 int r2 = 0;
126 124
127 r1 = READ_ONCE(flag); 125 r1 = READ_ONCE(flag);
128 if (r1) 126 if (r1)
129 r2 = READ_ONCE(buf); 127 r2 = READ_ONCE(buf);
130 } 128 }
131 129
132 Here the P0() function represents the interrup 130 Here the P0() function represents the interrupt handler running on one
133 CPU and P1() represents the read() routine run 131 CPU and P1() represents the read() routine running on another. The
134 value 1 stored in buf represents input data co 132 value 1 stored in buf represents input data collected from the device.
135 Thus, P0 stores the data in buf and then sets 133 Thus, P0 stores the data in buf and then sets flag. Meanwhile, P1
136 reads flag into the private variable r1, and i 134 reads flag into the private variable r1, and if it is set, reads the
137 data from buf into a second private variable r 135 data from buf into a second private variable r2 for copying to
138 userspace. (Presumably if flag is not set the 136 userspace. (Presumably if flag is not set then the driver will wait a
139 while and try again.) 137 while and try again.)
140 138
141 This pattern of memory accesses, where one CPU 139 This pattern of memory accesses, where one CPU stores values to two
142 shared memory locations and another CPU loads 140 shared memory locations and another CPU loads from those locations in
143 the opposite order, is widely known as the "Me 141 the opposite order, is widely known as the "Message Passing" or MP
144 pattern. It is typical of memory access patte 142 pattern. It is typical of memory access patterns in the kernel.
145 143
146 Please note that this example code is a simpli 144 Please note that this example code is a simplified abstraction. Real
147 buffers are usually larger than a single integ 145 buffers are usually larger than a single integer, real device drivers
148 usually use sleep and wakeup mechanisms rather 146 usually use sleep and wakeup mechanisms rather than polling for I/O
149 completion, and real code generally doesn't bo 147 completion, and real code generally doesn't bother to copy values into
150 private variables before using them. All that 148 private variables before using them. All that is beside the point;
151 the idea here is simply to illustrate the over 149 the idea here is simply to illustrate the overall pattern of memory
152 accesses by the CPUs. 150 accesses by the CPUs.
153 151
154 A memory model will predict what values P1 mig 152 A memory model will predict what values P1 might obtain for its loads
155 from flag and buf, or equivalently, what value 153 from flag and buf, or equivalently, what values r1 and r2 might end up
156 with after the code has finished running. 154 with after the code has finished running.
157 155
158 Some predictions are trivial. For instance, n 156 Some predictions are trivial. For instance, no sane memory model would
159 predict that r1 = 42 or r2 = -7, because neith 157 predict that r1 = 42 or r2 = -7, because neither of those values ever
160 gets stored in flag or buf. 158 gets stored in flag or buf.
161 159
162 Some nontrivial predictions are nonetheless qu 160 Some nontrivial predictions are nonetheless quite simple. For
163 instance, P1 might run entirely before P0 begi 161 instance, P1 might run entirely before P0 begins, in which case r1 and
164 r2 will both be 0 at the end. Or P0 might run 162 r2 will both be 0 at the end. Or P0 might run entirely before P1
165 begins, in which case r1 and r2 will both be 1 163 begins, in which case r1 and r2 will both be 1.
166 164
167 The interesting predictions concern what might 165 The interesting predictions concern what might happen when the two
168 routines run concurrently. One possibility is 166 routines run concurrently. One possibility is that P1 runs after P0's
169 store to buf but before the store to flag. In 167 store to buf but before the store to flag. In this case, r1 and r2
170 will again both be 0. (If P1 had been designe 168 will again both be 0. (If P1 had been designed to read buf
171 unconditionally then we would instead have r1 169 unconditionally then we would instead have r1 = 0 and r2 = 1.)
172 170
173 However, the most interesting possibility is w 171 However, the most interesting possibility is where r1 = 1 and r2 = 0.
174 If this were to occur it would mean the driver 172 If this were to occur it would mean the driver contains a bug, because
175 incorrect data would get sent to the user: 0 i 173 incorrect data would get sent to the user: 0 instead of 1. As it
176 happens, the LKMM does predict this outcome ca 174 happens, the LKMM does predict this outcome can occur, and the example
177 driver code shown above is indeed buggy. 175 driver code shown above is indeed buggy.
178 176
179 177
180 A SELECTION OF MEMORY MODELS 178 A SELECTION OF MEMORY MODELS
181 ---------------------------- 179 ----------------------------
182 180
183 The first widely cited memory model, and the s 181 The first widely cited memory model, and the simplest to understand,
184 is Sequential Consistency. According to this 182 is Sequential Consistency. According to this model, systems behave as
185 if each CPU executed its instructions in order 183 if each CPU executed its instructions in order but with unspecified
186 timing. In other words, the instructions from 184 timing. In other words, the instructions from the various CPUs get
187 interleaved in a nondeterministic way, always 185 interleaved in a nondeterministic way, always according to some single
188 global order that agrees with the order of the 186 global order that agrees with the order of the instructions in the
189 program source for each CPU. The model says t 187 program source for each CPU. The model says that the value obtained
190 by each load is simply the value written by th 188 by each load is simply the value written by the most recently executed
191 store to the same memory location, from any CP 189 store to the same memory location, from any CPU.
192 190
193 For the MP example code shown above, Sequentia 191 For the MP example code shown above, Sequential Consistency predicts
194 that the undesired result r1 = 1, r2 = 0 canno 192 that the undesired result r1 = 1, r2 = 0 cannot occur. The reasoning
195 goes like this: 193 goes like this:
196 194
197 Since r1 = 1, P0 must store 1 to flag 195 Since r1 = 1, P0 must store 1 to flag before P1 loads 1 from
198 it, as loads can obtain values only fr 196 it, as loads can obtain values only from earlier stores.
199 197
200 P1 loads from flag before loading from 198 P1 loads from flag before loading from buf, since CPUs execute
201 their instructions in order. 199 their instructions in order.
202 200
203 P1 must load 0 from buf before P0 stor 201 P1 must load 0 from buf before P0 stores 1 to it; otherwise r2
204 would be 1 since a load obtains its va 202 would be 1 since a load obtains its value from the most recent
205 store to the same address. 203 store to the same address.
206 204
207 P0 stores 1 to buf before storing 1 to 205 P0 stores 1 to buf before storing 1 to flag, since it executes
208 its instructions in order. 206 its instructions in order.
209 207
210 Since an instruction (in this case, P0 !! 208 Since an instruction (in this case, P1's store to flag) cannot
211 execute before itself, the specified o 209 execute before itself, the specified outcome is impossible.
212 210
213 However, real computer hardware almost never f 211 However, real computer hardware almost never follows the Sequential
214 Consistency memory model; doing so would rule 212 Consistency memory model; doing so would rule out too many valuable
215 performance optimizations. On ARM and PowerPC 213 performance optimizations. On ARM and PowerPC architectures, for
216 instance, the MP example code really does some 214 instance, the MP example code really does sometimes yield r1 = 1 and
217 r2 = 0. 215 r2 = 0.
218 216
219 x86 and SPARC follow yet a different memory mo 217 x86 and SPARC follow yet a different memory model: TSO (Total Store
220 Ordering). This model predicts that the undes 218 Ordering). This model predicts that the undesired outcome for the MP
221 pattern cannot occur, but in other respects it 219 pattern cannot occur, but in other respects it differs from Sequential
222 Consistency. One example is the Store Buffer 220 Consistency. One example is the Store Buffer (SB) pattern, in which
223 each CPU stores to its own shared location and 221 each CPU stores to its own shared location and then loads from the
224 other CPU's location: 222 other CPU's location:
225 223
226 int x = 0, y = 0; 224 int x = 0, y = 0;
227 225
228 P0() 226 P0()
229 { 227 {
230 int r0; 228 int r0;
231 229
232 WRITE_ONCE(x, 1); 230 WRITE_ONCE(x, 1);
233 r0 = READ_ONCE(y); 231 r0 = READ_ONCE(y);
234 } 232 }
235 233
236 P1() 234 P1()
237 { 235 {
238 int r1; 236 int r1;
239 237
240 WRITE_ONCE(y, 1); 238 WRITE_ONCE(y, 1);
241 r1 = READ_ONCE(x); 239 r1 = READ_ONCE(x);
242 } 240 }
243 241
244 Sequential Consistency predicts that the outco 242 Sequential Consistency predicts that the outcome r0 = 0, r1 = 0 is
245 impossible. (Exercise: Figure out the reasoni 243 impossible. (Exercise: Figure out the reasoning.) But TSO allows
246 this outcome to occur, and in fact it does som 244 this outcome to occur, and in fact it does sometimes occur on x86 and
247 SPARC systems. 245 SPARC systems.
248 246
249 The LKMM was inspired by the memory models fol 247 The LKMM was inspired by the memory models followed by PowerPC, ARM,
250 x86, Alpha, and other architectures. However, 248 x86, Alpha, and other architectures. However, it is different in
251 detail from each of them. 249 detail from each of them.
252 250
253 251
254 ORDERING AND CYCLES 252 ORDERING AND CYCLES
255 ------------------- 253 -------------------
256 254
257 Memory models are all about ordering. Often t 255 Memory models are all about ordering. Often this is temporal ordering
258 (i.e., the order in which certain events occur 256 (i.e., the order in which certain events occur) but it doesn't have to
259 be; consider for example the order of instruct 257 be; consider for example the order of instructions in a program's
260 source code. We saw above that Sequential Con 258 source code. We saw above that Sequential Consistency makes an
261 important assumption that CPUs execute instruc 259 important assumption that CPUs execute instructions in the same order
262 as those instructions occur in the code, and t 260 as those instructions occur in the code, and there are many other
263 instances of ordering playing central roles in 261 instances of ordering playing central roles in memory models.
264 262
265 The counterpart to ordering is a cycle. Order 263 The counterpart to ordering is a cycle. Ordering rules out cycles:
266 It's not possible to have X ordered before Y, 264 It's not possible to have X ordered before Y, Y ordered before Z, and
267 Z ordered before X, because this would mean th 265 Z ordered before X, because this would mean that X is ordered before
268 itself. The analysis of the MP example under 266 itself. The analysis of the MP example under Sequential Consistency
269 involved just such an impossible cycle: 267 involved just such an impossible cycle:
270 268
271 W: P0 stores 1 to flag executes befo 269 W: P0 stores 1 to flag executes before
272 X: P1 loads 1 from flag executes befo 270 X: P1 loads 1 from flag executes before
273 Y: P1 loads 0 from buf executes befo 271 Y: P1 loads 0 from buf executes before
274 Z: P0 stores 1 to buf executes befo 272 Z: P0 stores 1 to buf executes before
275 W: P0 stores 1 to flag. 273 W: P0 stores 1 to flag.
276 274
277 In short, if a memory model requires certain a 275 In short, if a memory model requires certain accesses to be ordered,
278 and a certain outcome for the loads in a piece 276 and a certain outcome for the loads in a piece of code can happen only
279 if those accesses would form a cycle, then the 277 if those accesses would form a cycle, then the memory model predicts
280 that outcome cannot occur. 278 that outcome cannot occur.
281 279
282 The LKMM is defined largely in terms of cycles 280 The LKMM is defined largely in terms of cycles, as we will see.
283 281
284 282
285 EVENTS 283 EVENTS
286 ------ 284 ------
287 285
288 The LKMM does not work directly with the C sta 286 The LKMM does not work directly with the C statements that make up
289 kernel source code. Instead it considers the 287 kernel source code. Instead it considers the effects of those
290 statements in a more abstract form, namely, ev 288 statements in a more abstract form, namely, events. The model
291 includes three types of events: 289 includes three types of events:
292 290
293 Read events correspond to loads from s 291 Read events correspond to loads from shared memory, such as
294 calls to READ_ONCE(), smp_load_acquire 292 calls to READ_ONCE(), smp_load_acquire(), or
295 rcu_dereference(). 293 rcu_dereference().
296 294
297 Write events correspond to stores to s 295 Write events correspond to stores to shared memory, such as
298 calls to WRITE_ONCE(), smp_store_relea 296 calls to WRITE_ONCE(), smp_store_release(), or atomic_set().
299 297
300 Fence events correspond to memory barr 298 Fence events correspond to memory barriers (also known as
301 fences), such as calls to smp_rmb() or 299 fences), such as calls to smp_rmb() or rcu_read_lock().
302 300
303 These categories are not exclusive; a read or 301 These categories are not exclusive; a read or write event can also be
304 a fence. This happens with functions like smp 302 a fence. This happens with functions like smp_load_acquire() or
305 spin_lock(). However, no single event can be 303 spin_lock(). However, no single event can be both a read and a write.
306 Atomic read-modify-write accesses, such as ato 304 Atomic read-modify-write accesses, such as atomic_inc() or xchg(),
307 correspond to a pair of events: a read followe 305 correspond to a pair of events: a read followed by a write. (The
308 write event is omitted for executions where it 306 write event is omitted for executions where it doesn't occur, such as
309 a cmpxchg() where the comparison fails.) 307 a cmpxchg() where the comparison fails.)
310 308
311 Other parts of the code, those which do not in 309 Other parts of the code, those which do not involve interaction with
312 shared memory, do not give rise to events. Th 310 shared memory, do not give rise to events. Thus, arithmetic and
313 logical computations, control-flow instruction 311 logical computations, control-flow instructions, or accesses to
314 private memory or CPU registers are not of cen 312 private memory or CPU registers are not of central interest to the
315 memory model. They only affect the model's pr 313 memory model. They only affect the model's predictions indirectly.
316 For example, an arithmetic computation might d 314 For example, an arithmetic computation might determine the value that
317 gets stored to a shared memory location (or in 315 gets stored to a shared memory location (or in the case of an array
318 index, the address where the value gets stored 316 index, the address where the value gets stored), but the memory model
319 is concerned only with the store itself -- its 317 is concerned only with the store itself -- its value and its address
320 -- not the computation leading up to it. 318 -- not the computation leading up to it.
321 319
322 Events in the LKMM can be linked by various re 320 Events in the LKMM can be linked by various relations, which we will
323 describe in the following sections. The memor 321 describe in the following sections. The memory model requires certain
324 of these relations to be orderings, that is, i 322 of these relations to be orderings, that is, it requires them not to
325 have any cycles. 323 have any cycles.
326 324
327 325
328 THE PROGRAM ORDER RELATION: po AND po-loc 326 THE PROGRAM ORDER RELATION: po AND po-loc
329 ----------------------------------------- 327 -----------------------------------------
330 328
331 The most important relation between events is 329 The most important relation between events is program order (po). You
332 can think of it as the order in which statemen 330 can think of it as the order in which statements occur in the source
333 code after branches are taken into account and 331 code after branches are taken into account and loops have been
334 unrolled. A better description might be the o 332 unrolled. A better description might be the order in which
335 instructions are presented to a CPU's executio 333 instructions are presented to a CPU's execution unit. Thus, we say
336 that X is po-before Y (written as "X ->po Y" i 334 that X is po-before Y (written as "X ->po Y" in formulas) if X occurs
337 before Y in the instruction stream. 335 before Y in the instruction stream.
338 336
339 This is inherently a single-CPU relation; two 337 This is inherently a single-CPU relation; two instructions executing
340 on different CPUs are never linked by po. Als 338 on different CPUs are never linked by po. Also, it is by definition
341 an ordering so it cannot have any cycles. 339 an ordering so it cannot have any cycles.
342 340
343 po-loc is a sub-relation of po. It links two 341 po-loc is a sub-relation of po. It links two memory accesses when the
344 first comes before the second in program order 342 first comes before the second in program order and they access the
345 same memory location (the "-loc" suffix). 343 same memory location (the "-loc" suffix).
346 344
347 Although this may seem straightforward, there 345 Although this may seem straightforward, there is one subtle aspect to
348 program order we need to explain. The LKMM wa 346 program order we need to explain. The LKMM was inspired by low-level
349 architectural memory models which describe the 347 architectural memory models which describe the behavior of machine
350 code, and it retains their outlook to a consid 348 code, and it retains their outlook to a considerable extent. The
351 read, write, and fence events used by the mode 349 read, write, and fence events used by the model are close in spirit to
352 individual machine instructions. Nevertheless 350 individual machine instructions. Nevertheless, the LKMM describes
353 kernel code written in C, and the mapping from 351 kernel code written in C, and the mapping from C to machine code can
354 be extremely complex. 352 be extremely complex.
355 353
356 Optimizing compilers have great freedom in the 354 Optimizing compilers have great freedom in the way they translate
357 source code to object code. They are allowed 355 source code to object code. They are allowed to apply transformations
358 that add memory accesses, eliminate accesses, 356 that add memory accesses, eliminate accesses, combine them, split them
359 into pieces, or move them around. The use of !! 357 into pieces, or move them around. Faced with all these possibilities,
360 or one of the other atomic or synchronization !! 358 the LKMM basically gives up. It insists that the code it analyzes
361 large number of compiler optimizations. In pa !! 359 must contain no ordinary accesses to shared memory; all accesses must
362 that the compiler will not remove such accesse !! 360 be performed using READ_ONCE(), WRITE_ONCE(), or one of the other
363 (unless it can prove the accesses will never b !! 361 atomic or synchronization primitives. These primitives prevent a
364 change the order in which they occur in the co !! 362 large number of compiler optimizations. In particular, it is
365 by the C standard), and it will not introduce !! 363 guaranteed that the compiler will not remove such accesses from the
366 !! 364 generated code (unless it can prove the accesses will never be
367 The MP and SB examples above used READ_ONCE() !! 365 executed), it will not change the order in which they occur in the
368 than ordinary memory accesses. Thanks to this !! 366 code (within limits imposed by the C standard), and it will not
369 that in the MP example, the compiler won't reo !! 367 introduce extraneous accesses.
370 buf and P0's write event to flag, and similarl !! 368
371 memory accesses in the examples. !! 369 This explains why the MP and SB examples above used READ_ONCE() and
372 !! 370 WRITE_ONCE() rather than ordinary memory accesses. Thanks to this
373 Since private variables are not shared between !! 371 usage, we can be certain that in the MP example, P0's write event to
374 accessed normally without READ_ONCE() or WRITE !! 372 buf really is po-before its write event to flag, and similarly for the
375 need not even be stored in normal memory at al !! 373 other shared memory accesses in the examples.
376 private variable could be stored in a CPU regi !! 374
377 that these variables have names starting with !! 375 Private variables are not subject to this restriction. Since they are
>> 376 not shared between CPUs, they can be accessed normally without
>> 377 READ_ONCE() or WRITE_ONCE(), and there will be no ill effects. In
>> 378 fact, they need not even be stored in normal memory at all -- in
>> 379 principle a private variable could be stored in a CPU register (hence
>> 380 the convention that these variables have names starting with the
>> 381 letter 'r').
378 382
379 383
380 A WARNING 384 A WARNING
381 --------- 385 ---------
382 386
383 The protections provided by READ_ONCE(), WRITE 387 The protections provided by READ_ONCE(), WRITE_ONCE(), and others are
384 not perfect; and under some circumstances it i 388 not perfect; and under some circumstances it is possible for the
385 compiler to undermine the memory model. Here 389 compiler to undermine the memory model. Here is an example. Suppose
386 both branches of an "if" statement store the s 390 both branches of an "if" statement store the same value to the same
387 location: 391 location:
388 392
389 r1 = READ_ONCE(x); 393 r1 = READ_ONCE(x);
390 if (r1) { 394 if (r1) {
391 WRITE_ONCE(y, 2); 395 WRITE_ONCE(y, 2);
392 ... /* do something */ 396 ... /* do something */
393 } else { 397 } else {
394 WRITE_ONCE(y, 2); 398 WRITE_ONCE(y, 2);
395 ... /* do something else */ 399 ... /* do something else */
396 } 400 }
397 401
398 For this code, the LKMM predicts that the load 402 For this code, the LKMM predicts that the load from x will always be
399 executed before either of the stores to y. Ho 403 executed before either of the stores to y. However, a compiler could
400 lift the stores out of the conditional, transf 404 lift the stores out of the conditional, transforming the code into
401 something resembling: 405 something resembling:
402 406
403 r1 = READ_ONCE(x); 407 r1 = READ_ONCE(x);
404 WRITE_ONCE(y, 2); 408 WRITE_ONCE(y, 2);
405 if (r1) { 409 if (r1) {
406 ... /* do something */ 410 ... /* do something */
407 } else { 411 } else {
408 ... /* do something else */ 412 ... /* do something else */
409 } 413 }
410 414
411 Given this version of the code, the LKMM would 415 Given this version of the code, the LKMM would predict that the load
412 from x could be executed after the store to y. 416 from x could be executed after the store to y. Thus, the memory
413 model's original prediction could be invalidat 417 model's original prediction could be invalidated by the compiler.
414 418
415 Another issue arises from the fact that in C, 419 Another issue arises from the fact that in C, arguments to many
416 operators and function calls can be evaluated 420 operators and function calls can be evaluated in any order. For
417 example: 421 example:
418 422
419 r1 = f(5) + g(6); 423 r1 = f(5) + g(6);
420 424
421 The object code might call f(5) either before 425 The object code might call f(5) either before or after g(6); the
422 memory model cannot assume there is a fixed pr 426 memory model cannot assume there is a fixed program order relation
423 between them. (In fact, if the function calls !! 427 between them. (In fact, if the functions are inlined then the
424 compiler might even interleave their object co 428 compiler might even interleave their object code.)
425 429
426 430
427 DEPENDENCY RELATIONS: data, addr, and ctrl 431 DEPENDENCY RELATIONS: data, addr, and ctrl
428 ------------------------------------------ 432 ------------------------------------------
429 433
430 We say that two events are linked by a depende 434 We say that two events are linked by a dependency relation when the
431 execution of the second event depends in some 435 execution of the second event depends in some way on a value obtained
432 from memory by the first. The first event mus 436 from memory by the first. The first event must be a read, and the
433 value it obtains must somehow affect what the 437 value it obtains must somehow affect what the second event does.
434 There are three kinds of dependencies: data, a 438 There are three kinds of dependencies: data, address (addr), and
435 control (ctrl). 439 control (ctrl).
436 440
437 A read and a write event are linked by a data 441 A read and a write event are linked by a data dependency if the value
438 obtained by the read affects the value stored 442 obtained by the read affects the value stored by the write. As a very
439 simple example: 443 simple example:
440 444
441 int x, y; 445 int x, y;
442 446
443 r1 = READ_ONCE(x); 447 r1 = READ_ONCE(x);
444 WRITE_ONCE(y, r1 + 5); 448 WRITE_ONCE(y, r1 + 5);
445 449
446 The value stored by the WRITE_ONCE obviously d 450 The value stored by the WRITE_ONCE obviously depends on the value
447 loaded by the READ_ONCE. Such dependencies ca 451 loaded by the READ_ONCE. Such dependencies can wind through
448 arbitrarily complicated computations, and a wr 452 arbitrarily complicated computations, and a write can depend on the
449 values of multiple reads. 453 values of multiple reads.
450 454
451 A read event and another memory access event a 455 A read event and another memory access event are linked by an address
452 dependency if the value obtained by the read a 456 dependency if the value obtained by the read affects the location
453 accessed by the other event. The second event 457 accessed by the other event. The second event can be either a read or
454 a write. Here's another simple example: 458 a write. Here's another simple example:
455 459
456 int a[20]; 460 int a[20];
457 int i; 461 int i;
458 462
459 r1 = READ_ONCE(i); 463 r1 = READ_ONCE(i);
460 r2 = READ_ONCE(a[r1]); 464 r2 = READ_ONCE(a[r1]);
461 465
462 Here the location accessed by the second READ_ 466 Here the location accessed by the second READ_ONCE() depends on the
463 index value loaded by the first. Pointer indi 467 index value loaded by the first. Pointer indirection also gives rise
464 to address dependencies, since the address of 468 to address dependencies, since the address of a location accessed
465 through a pointer will depend on the value rea 469 through a pointer will depend on the value read earlier from that
466 pointer. 470 pointer.
467 471
468 Finally, a read event X and a write event Y ar !! 472 Finally, a read event and another memory access event are linked by a
469 dependency if Y syntactically lies within an a !! 473 control dependency if the value obtained by the read affects whether
470 X affects the evaluation of the if condition v !! 474 the second event is executed at all. Simple example:
471 dependency (or similarly for a switch statemen <<
472 475
473 int x, y; 476 int x, y;
474 477
475 r1 = READ_ONCE(x); 478 r1 = READ_ONCE(x);
476 if (r1) 479 if (r1)
477 WRITE_ONCE(y, 1984); 480 WRITE_ONCE(y, 1984);
478 481
479 Execution of the WRITE_ONCE() is controlled by 482 Execution of the WRITE_ONCE() is controlled by a conditional expression
480 which depends on the value obtained by the REA 483 which depends on the value obtained by the READ_ONCE(); hence there is
481 a control dependency from the load to the stor 484 a control dependency from the load to the store.
482 485
483 It should be pretty obvious that events can on 486 It should be pretty obvious that events can only depend on reads that
484 come earlier in program order. Symbolically, 487 come earlier in program order. Symbolically, if we have R ->data X,
485 R ->addr X, or R ->ctrl X (where R is a read e 488 R ->addr X, or R ->ctrl X (where R is a read event), then we must also
486 have R ->po X. It wouldn't make sense for a c 489 have R ->po X. It wouldn't make sense for a computation to depend
487 somehow on a value that doesn't get loaded fro 490 somehow on a value that doesn't get loaded from shared memory until
488 later in the code! 491 later in the code!
489 492
490 Here's a trick question: When is a dependency <<
491 When it is purely syntactic rather than semant <<
492 between two accesses is purely syntactic if th <<
493 actually depend on the result of the first. H <<
494 <<
495 r1 = READ_ONCE(x); <<
496 WRITE_ONCE(y, r1 * 0); <<
497 <<
498 There appears to be a data dependency from the <<
499 of y, since the value to be stored is computed <<
500 loaded. But in fact, the value stored does no <<
501 anything since it will always be 0. Thus the <<
502 syntactic (it appears to exist in the code) bu <<
503 second access will always be the same, regardl <<
504 first access). Given code like this, a compil <<
505 the value returned by the load from x, which w <<
506 any dependency. (The compiler is not permitte <<
507 the load generated for a READ_ONCE() -- that's <<
508 properties of READ_ONCE() -- but it is allowed <<
509 value.) <<
510 <<
511 It's natural to object that no one in their ri <<
512 code like the above. However, macro expansion <<
513 to this sort of thing, in ways that often are <<
514 programmer. <<
515 <<
516 Another mechanism that can lead to purely synt <<
517 related to the notion of "undefined behavior". <<
518 behaviors are called "undefined" in the C lang <<
519 which means that when they occur there are no <<
520 the outcome. Consider the following example: <<
521 <<
522 int a[1]; <<
523 int i; <<
524 <<
525 r1 = READ_ONCE(i); <<
526 r2 = READ_ONCE(a[r1]); <<
527 <<
528 Access beyond the end or before the beginning <<
529 of undefined behavior. Therefore the compiler <<
530 about what will happen if r1 is nonzero, and i <<
531 will always be zero regardless of the value ac <<
532 (If the assumption turns out to be wrong the r <<
533 be undefined anyway, so the compiler doesn't c <<
534 from the load can be discarded, breaking the a <<
535 <<
536 The LKMM is unaware that purely syntactic depe <<
537 from semantic dependencies and therefore mista <<
538 accesses in the two examples above will be ord <<
539 example of how the compiler can undermine the <<
540 <<
541 493
542 THE READS-FROM RELATION: rf, rfi, and rfe 494 THE READS-FROM RELATION: rf, rfi, and rfe
543 ----------------------------------------- 495 -----------------------------------------
544 496
545 The reads-from relation (rf) links a write eve 497 The reads-from relation (rf) links a write event to a read event when
546 the value loaded by the read is the value that 498 the value loaded by the read is the value that was stored by the
547 write. In colloquial terms, the load "reads f 499 write. In colloquial terms, the load "reads from" the store. We
548 write W ->rf R to indicate that the load R rea 500 write W ->rf R to indicate that the load R reads from the store W. We
549 further distinguish the cases where the load a 501 further distinguish the cases where the load and the store occur on
550 the same CPU (internal reads-from, or rfi) and 502 the same CPU (internal reads-from, or rfi) and where they occur on
551 different CPUs (external reads-from, or rfe). 503 different CPUs (external reads-from, or rfe).
552 504
553 For our purposes, a memory location's initial 505 For our purposes, a memory location's initial value is treated as
554 though it had been written there by an imagina 506 though it had been written there by an imaginary initial store that
555 executes on a separate CPU before the main pro !! 507 executes on a separate CPU before the program runs.
556 508
557 Usage of the rf relation implicitly assumes th 509 Usage of the rf relation implicitly assumes that loads will always
558 read from a single store. It doesn't apply pr 510 read from a single store. It doesn't apply properly in the presence
559 of load-tearing, where a load obtains some of 511 of load-tearing, where a load obtains some of its bits from one store
560 and some of them from another store. Fortunat 512 and some of them from another store. Fortunately, use of READ_ONCE()
561 and WRITE_ONCE() will prevent load-tearing; it 513 and WRITE_ONCE() will prevent load-tearing; it's not possible to have:
562 514
563 int x = 0; 515 int x = 0;
564 516
565 P0() 517 P0()
566 { 518 {
567 WRITE_ONCE(x, 0x1234); 519 WRITE_ONCE(x, 0x1234);
568 } 520 }
569 521
570 P1() 522 P1()
571 { 523 {
572 int r1; 524 int r1;
573 525
574 r1 = READ_ONCE(x); 526 r1 = READ_ONCE(x);
575 } 527 }
576 528
577 and end up with r1 = 0x1200 (partly from x's i 529 and end up with r1 = 0x1200 (partly from x's initial value and partly
578 from the value stored by P0). 530 from the value stored by P0).
579 531
580 On the other hand, load-tearing is unavoidable 532 On the other hand, load-tearing is unavoidable when mixed-size
581 accesses are used. Consider this example: 533 accesses are used. Consider this example:
582 534
583 union { 535 union {
584 u32 w; 536 u32 w;
585 u16 h[2]; 537 u16 h[2];
586 } x; 538 } x;
587 539
588 P0() 540 P0()
589 { 541 {
590 WRITE_ONCE(x.h[0], 0x1234); 542 WRITE_ONCE(x.h[0], 0x1234);
591 WRITE_ONCE(x.h[1], 0x5678); 543 WRITE_ONCE(x.h[1], 0x5678);
592 } 544 }
593 545
594 P1() 546 P1()
595 { 547 {
596 int r1; 548 int r1;
597 549
598 r1 = READ_ONCE(x.w); 550 r1 = READ_ONCE(x.w);
599 } 551 }
600 552
601 If r1 = 0x56781234 (little-endian!) at the end 553 If r1 = 0x56781234 (little-endian!) at the end, then P1 must have read
602 from both of P0's stores. It is possible to h 554 from both of P0's stores. It is possible to handle mixed-size and
603 unaligned accesses in a memory model, but the 555 unaligned accesses in a memory model, but the LKMM currently does not
604 attempt to do so. It requires all accesses to 556 attempt to do so. It requires all accesses to be properly aligned and
605 of the location's actual size. 557 of the location's actual size.
606 558
607 559
608 CACHE COHERENCE AND THE COHERENCE ORDER RELATI 560 CACHE COHERENCE AND THE COHERENCE ORDER RELATION: co, coi, and coe
609 ---------------------------------------------- 561 ------------------------------------------------------------------
610 562
611 Cache coherence is a general principle requiri 563 Cache coherence is a general principle requiring that in a
612 multi-processor system, the CPUs must share a 564 multi-processor system, the CPUs must share a consistent view of the
613 memory contents. Specifically, it requires th 565 memory contents. Specifically, it requires that for each location in
614 shared memory, the stores to that location mus 566 shared memory, the stores to that location must form a single global
615 ordering which all the CPUs agree on (the cohe 567 ordering which all the CPUs agree on (the coherence order), and this
616 ordering must be consistent with the program o 568 ordering must be consistent with the program order for accesses to
617 that location. 569 that location.
618 570
619 To put it another way, for any variable x, the 571 To put it another way, for any variable x, the coherence order (co) of
620 the stores to x is simply the order in which t 572 the stores to x is simply the order in which the stores overwrite one
621 another. The imaginary store which establishe 573 another. The imaginary store which establishes x's initial value
622 comes first in the coherence order; the store 574 comes first in the coherence order; the store which directly
623 overwrites the initial value comes second; the 575 overwrites the initial value comes second; the store which overwrites
624 that value comes third, and so on. 576 that value comes third, and so on.
625 577
626 You can think of the coherence order as being 578 You can think of the coherence order as being the order in which the
627 stores reach x's location in memory (or if you 579 stores reach x's location in memory (or if you prefer a more
628 hardware-centric view, the order in which the 580 hardware-centric view, the order in which the stores get written to
629 x's cache line). We write W ->co W' if W come 581 x's cache line). We write W ->co W' if W comes before W' in the
630 coherence order, that is, if the value stored 582 coherence order, that is, if the value stored by W gets overwritten,
631 directly or indirectly, by the value stored by 583 directly or indirectly, by the value stored by W'.
632 584
633 Coherence order is required to be consistent w 585 Coherence order is required to be consistent with program order. This
634 requirement takes the form of four coherency r 586 requirement takes the form of four coherency rules:
635 587
636 Write-write coherence: If W ->po-loc W 588 Write-write coherence: If W ->po-loc W' (i.e., W comes before
637 W' in program order and they access th 589 W' in program order and they access the same location), where W
638 and W' are two stores, then W ->co W'. 590 and W' are two stores, then W ->co W'.
639 591
640 Write-read coherence: If W ->po-loc R, 592 Write-read coherence: If W ->po-loc R, where W is a store and R
641 is a load, then R must read from W or 593 is a load, then R must read from W or from some other store
642 which comes after W in the coherence o 594 which comes after W in the coherence order.
643 595
644 Read-write coherence: If R ->po-loc W, 596 Read-write coherence: If R ->po-loc W, where R is a load and W
645 is a store, then the store which R rea 597 is a store, then the store which R reads from must come before
646 W in the coherence order. 598 W in the coherence order.
647 599
648 Read-read coherence: If R ->po-loc R', 600 Read-read coherence: If R ->po-loc R', where R and R' are two
649 loads, then either they read from the 601 loads, then either they read from the same store or else the
650 store read by R comes before the store 602 store read by R comes before the store read by R' in the
651 coherence order. 603 coherence order.
652 604
653 This is sometimes referred to as sequential co 605 This is sometimes referred to as sequential consistency per variable,
654 because it means that the accesses to any sing 606 because it means that the accesses to any single memory location obey
655 the rules of the Sequential Consistency memory 607 the rules of the Sequential Consistency memory model. (According to
656 Wikipedia, sequential consistency per variable 608 Wikipedia, sequential consistency per variable and cache coherence
657 mean the same thing except that cache coherenc 609 mean the same thing except that cache coherence includes an extra
658 requirement that every store eventually become 610 requirement that every store eventually becomes visible to every CPU.)
659 611
660 Any reasonable memory model will include cache 612 Any reasonable memory model will include cache coherence. Indeed, our
661 expectation of cache coherence is so deeply in 613 expectation of cache coherence is so deeply ingrained that violations
662 of its requirements look more like hardware bu 614 of its requirements look more like hardware bugs than programming
663 errors: 615 errors:
664 616
665 int x; 617 int x;
666 618
667 P0() 619 P0()
668 { 620 {
669 WRITE_ONCE(x, 17); 621 WRITE_ONCE(x, 17);
670 WRITE_ONCE(x, 23); 622 WRITE_ONCE(x, 23);
671 } 623 }
672 624
673 If the final value stored in x after this code 625 If the final value stored in x after this code ran was 17, you would
674 think your computer was broken. It would be a 626 think your computer was broken. It would be a violation of the
675 write-write coherence rule: Since the store of 627 write-write coherence rule: Since the store of 23 comes later in
676 program order, it must also come later in x's 628 program order, it must also come later in x's coherence order and
677 thus must overwrite the store of 17. 629 thus must overwrite the store of 17.
678 630
679 int x = 0; 631 int x = 0;
680 632
681 P0() 633 P0()
682 { 634 {
683 int r1; 635 int r1;
684 636
685 r1 = READ_ONCE(x); 637 r1 = READ_ONCE(x);
686 WRITE_ONCE(x, 666); 638 WRITE_ONCE(x, 666);
687 } 639 }
688 640
689 If r1 = 666 at the end, this would violate the 641 If r1 = 666 at the end, this would violate the read-write coherence
690 rule: The READ_ONCE() load comes before the WR 642 rule: The READ_ONCE() load comes before the WRITE_ONCE() store in
691 program order, so it must not read from that s 643 program order, so it must not read from that store but rather from one
692 coming earlier in the coherence order (in this 644 coming earlier in the coherence order (in this case, x's initial
693 value). 645 value).
694 646
695 int x = 0; 647 int x = 0;
696 648
697 P0() 649 P0()
698 { 650 {
699 WRITE_ONCE(x, 5); 651 WRITE_ONCE(x, 5);
700 } 652 }
701 653
702 P1() 654 P1()
703 { 655 {
704 int r1, r2; 656 int r1, r2;
705 657
706 r1 = READ_ONCE(x); 658 r1 = READ_ONCE(x);
707 r2 = READ_ONCE(x); 659 r2 = READ_ONCE(x);
708 } 660 }
709 661
710 If r1 = 5 (reading from P0's store) and r2 = 0 662 If r1 = 5 (reading from P0's store) and r2 = 0 (reading from the
711 imaginary store which establishes x's initial 663 imaginary store which establishes x's initial value) at the end, this
712 would violate the read-read coherence rule: Th 664 would violate the read-read coherence rule: The r1 load comes before
713 the r2 load in program order, so it must not r 665 the r2 load in program order, so it must not read from a store that
714 comes later in the coherence order. 666 comes later in the coherence order.
715 667
716 (As a minor curiosity, if this code had used n 668 (As a minor curiosity, if this code had used normal loads instead of
717 READ_ONCE() in P1, on Itanium it sometimes cou 669 READ_ONCE() in P1, on Itanium it sometimes could end up with r1 = 5
718 and r2 = 0! This results from parallel execut 670 and r2 = 0! This results from parallel execution of the operations
719 encoded in Itanium's Very-Long-Instruction-Wor 671 encoded in Itanium's Very-Long-Instruction-Word format, and it is yet
720 another motivation for using READ_ONCE() when 672 another motivation for using READ_ONCE() when accessing shared memory
721 locations.) 673 locations.)
722 674
723 Just like the po relation, co is inherently an 675 Just like the po relation, co is inherently an ordering -- it is not
724 possible for a store to directly or indirectly 676 possible for a store to directly or indirectly overwrite itself! And
725 just like with the rf relation, we distinguish 677 just like with the rf relation, we distinguish between stores that
726 occur on the same CPU (internal coherence orde 678 occur on the same CPU (internal coherence order, or coi) and stores
727 that occur on different CPUs (external coheren 679 that occur on different CPUs (external coherence order, or coe).
728 680
729 On the other hand, stores to different memory 681 On the other hand, stores to different memory locations are never
730 related by co, just as instructions on differe 682 related by co, just as instructions on different CPUs are never
731 related by po. Coherence order is strictly pe 683 related by po. Coherence order is strictly per-location, or if you
732 prefer, each location has its own independent 684 prefer, each location has its own independent coherence order.
733 685
734 686
735 THE FROM-READS RELATION: fr, fri, and fre 687 THE FROM-READS RELATION: fr, fri, and fre
736 ----------------------------------------- 688 -----------------------------------------
737 689
738 The from-reads relation (fr) can be a little d 690 The from-reads relation (fr) can be a little difficult for people to
739 grok. It describes the situation where a load 691 grok. It describes the situation where a load reads a value that gets
740 overwritten by a store. In other words, we ha 692 overwritten by a store. In other words, we have R ->fr W when the
741 value that R reads is overwritten (directly or 693 value that R reads is overwritten (directly or indirectly) by W, or
742 equivalently, when R reads from a store which 694 equivalently, when R reads from a store which comes earlier than W in
743 the coherence order. 695 the coherence order.
744 696
745 For example: 697 For example:
746 698
747 int x = 0; 699 int x = 0;
748 700
749 P0() 701 P0()
750 { 702 {
751 int r1; 703 int r1;
752 704
753 r1 = READ_ONCE(x); 705 r1 = READ_ONCE(x);
754 WRITE_ONCE(x, 2); 706 WRITE_ONCE(x, 2);
755 } 707 }
756 708
757 The value loaded from x will be 0 (assuming ca 709 The value loaded from x will be 0 (assuming cache coherence!), and it
758 gets overwritten by the value 2. Thus there i 710 gets overwritten by the value 2. Thus there is an fr link from the
759 READ_ONCE() to the WRITE_ONCE(). If the code 711 READ_ONCE() to the WRITE_ONCE(). If the code contained any later
760 stores to x, there would also be fr links from 712 stores to x, there would also be fr links from the READ_ONCE() to
761 them. 713 them.
762 714
763 As with rf, rfi, and rfe, we subdivide the fr 715 As with rf, rfi, and rfe, we subdivide the fr relation into fri (when
764 the load and the store are on the same CPU) an 716 the load and the store are on the same CPU) and fre (when they are on
765 different CPUs). 717 different CPUs).
766 718
767 Note that the fr relation is determined entire 719 Note that the fr relation is determined entirely by the rf and co
768 relations; it is not independent. Given a rea 720 relations; it is not independent. Given a read event R and a write
769 event W for the same location, we will have R 721 event W for the same location, we will have R ->fr W if and only if
770 the write which R reads from is co-before W. 722 the write which R reads from is co-before W. In symbols,
771 723
772 (R ->fr W) := (there exists W' with W' 724 (R ->fr W) := (there exists W' with W' ->rf R and W' ->co W).
773 725
774 726
775 AN OPERATIONAL MODEL 727 AN OPERATIONAL MODEL
776 -------------------- 728 --------------------
777 729
778 The LKMM is based on various operational memor 730 The LKMM is based on various operational memory models, meaning that
779 the models arise from an abstract view of how 731 the models arise from an abstract view of how a computer system
780 operates. Here are the main ideas, as incorpo 732 operates. Here are the main ideas, as incorporated into the LKMM.
781 733
782 The system as a whole is divided into the CPUs 734 The system as a whole is divided into the CPUs and a memory subsystem.
783 The CPUs are responsible for executing instruc 735 The CPUs are responsible for executing instructions (not necessarily
784 in program order), and they communicate with t 736 in program order), and they communicate with the memory subsystem.
785 For the most part, executing an instruction re 737 For the most part, executing an instruction requires a CPU to perform
786 only internal operations. However, loads, sto 738 only internal operations. However, loads, stores, and fences involve
787 more. 739 more.
788 740
789 When CPU C executes a store instruction, it te 741 When CPU C executes a store instruction, it tells the memory subsystem
790 to store a certain value at a certain location 742 to store a certain value at a certain location. The memory subsystem
791 propagates the store to all the other CPUs as 743 propagates the store to all the other CPUs as well as to RAM. (As a
792 special case, we say that the store propagates 744 special case, we say that the store propagates to its own CPU at the
793 time it is executed.) The memory subsystem al 745 time it is executed.) The memory subsystem also determines where the
794 store falls in the location's coherence order. 746 store falls in the location's coherence order. In particular, it must
795 arrange for the store to be co-later than (i.e 747 arrange for the store to be co-later than (i.e., to overwrite) any
796 other store to the same location which has alr 748 other store to the same location which has already propagated to CPU C.
797 749
798 When a CPU executes a load instruction R, it f 750 When a CPU executes a load instruction R, it first checks to see
799 whether there are any as-yet unexecuted store 751 whether there are any as-yet unexecuted store instructions, for the
800 same location, that come before R in program o 752 same location, that come before R in program order. If there are, it
801 uses the value of the po-latest such store as 753 uses the value of the po-latest such store as the value obtained by R,
802 and we say that the store's value is forwarded 754 and we say that the store's value is forwarded to R. Otherwise, the
803 CPU asks the memory subsystem for the value to 755 CPU asks the memory subsystem for the value to load and we say that R
804 is satisfied from memory. The memory subsyste 756 is satisfied from memory. The memory subsystem hands back the value
805 of the co-latest store to the location in ques 757 of the co-latest store to the location in question which has already
806 propagated to that CPU. 758 propagated to that CPU.
807 759
808 (In fact, the picture needs to be a little mor 760 (In fact, the picture needs to be a little more complicated than this.
809 CPUs have local caches, and propagating a stor 761 CPUs have local caches, and propagating a store to a CPU really means
810 propagating it to the CPU's local cache. A lo 762 propagating it to the CPU's local cache. A local cache can take some
811 time to process the stores that it receives, a 763 time to process the stores that it receives, and a store can't be used
812 to satisfy one of the CPU's loads until it has 764 to satisfy one of the CPU's loads until it has been processed. On
813 most architectures, the local caches process s 765 most architectures, the local caches process stores in
814 First-In-First-Out order, and consequently the 766 First-In-First-Out order, and consequently the processing delay
815 doesn't matter for the memory model. But on A 767 doesn't matter for the memory model. But on Alpha, the local caches
816 have a partitioned design that results in non- 768 have a partitioned design that results in non-FIFO behavior. We will
817 discuss this in more detail later.) 769 discuss this in more detail later.)
818 770
819 Note that load instructions may be executed sp 771 Note that load instructions may be executed speculatively and may be
820 restarted under certain circumstances. The me 772 restarted under certain circumstances. The memory model ignores these
821 premature executions; we simply say that the l 773 premature executions; we simply say that the load executes at the
822 final time it is forwarded or satisfied. 774 final time it is forwarded or satisfied.
823 775
824 Executing a fence (or memory barrier) instruct 776 Executing a fence (or memory barrier) instruction doesn't require a
825 CPU to do anything special other than informin 777 CPU to do anything special other than informing the memory subsystem
826 about the fence. However, fences do constrain 778 about the fence. However, fences do constrain the way CPUs and the
827 memory subsystem handle other instructions, in 779 memory subsystem handle other instructions, in two respects.
828 780
829 First, a fence forces the CPU to execute vario 781 First, a fence forces the CPU to execute various instructions in
830 program order. Exactly which instructions are 782 program order. Exactly which instructions are ordered depends on the
831 type of fence: 783 type of fence:
832 784
833 Strong fences, including smp_mb() and 785 Strong fences, including smp_mb() and synchronize_rcu(), force
834 the CPU to execute all po-earlier inst 786 the CPU to execute all po-earlier instructions before any
835 po-later instructions; 787 po-later instructions;
836 788
837 smp_rmb() forces the CPU to execute al 789 smp_rmb() forces the CPU to execute all po-earlier loads
838 before any po-later loads; 790 before any po-later loads;
839 791
840 smp_wmb() forces the CPU to execute al 792 smp_wmb() forces the CPU to execute all po-earlier stores
841 before any po-later stores; 793 before any po-later stores;
842 794
843 Acquire fences, such as smp_load_acqui 795 Acquire fences, such as smp_load_acquire(), force the CPU to
844 execute the load associated with the f 796 execute the load associated with the fence (e.g., the load
845 part of an smp_load_acquire()) before 797 part of an smp_load_acquire()) before any po-later
846 instructions; 798 instructions;
847 799
848 Release fences, such as smp_store_rele 800 Release fences, such as smp_store_release(), force the CPU to
849 execute all po-earlier instructions be 801 execute all po-earlier instructions before the store
850 associated with the fence (e.g., the s 802 associated with the fence (e.g., the store part of an
851 smp_store_release()). 803 smp_store_release()).
852 804
853 Second, some types of fence affect the way the 805 Second, some types of fence affect the way the memory subsystem
854 propagates stores. When a fence instruction i 806 propagates stores. When a fence instruction is executed on CPU C:
855 807
856 For each other CPU C', smp_wmb() force 808 For each other CPU C', smp_wmb() forces all po-earlier stores
857 on C to propagate to C' before any po- 809 on C to propagate to C' before any po-later stores do.
858 810
859 For each other CPU C', any store which 811 For each other CPU C', any store which propagates to C before
860 a release fence is executed (including 812 a release fence is executed (including all po-earlier
861 stores executed on C) is forced to pro 813 stores executed on C) is forced to propagate to C' before the
862 store associated with the release fenc 814 store associated with the release fence does.
863 815
864 Any store which propagates to C before 816 Any store which propagates to C before a strong fence is
865 executed (including all po-earlier sto 817 executed (including all po-earlier stores on C) is forced to
866 propagate to all other CPUs before any 818 propagate to all other CPUs before any instructions po-after
867 the strong fence are executed on C. 819 the strong fence are executed on C.
868 820
869 The propagation ordering enforced by release f 821 The propagation ordering enforced by release fences and strong fences
870 affects stores from other CPUs that propagate 822 affects stores from other CPUs that propagate to CPU C before the
871 fence is executed, as well as stores that are 823 fence is executed, as well as stores that are executed on C before the
872 fence. We describe this property by saying th 824 fence. We describe this property by saying that release fences and
873 strong fences are A-cumulative. By contrast, 825 strong fences are A-cumulative. By contrast, smp_wmb() fences are not
874 A-cumulative; they only affect the propagation 826 A-cumulative; they only affect the propagation of stores that are
875 executed on C before the fence (i.e., those wh 827 executed on C before the fence (i.e., those which precede the fence in
876 program order). 828 program order).
877 829
878 rcu_read_lock(), rcu_read_unlock(), and synchr 830 rcu_read_lock(), rcu_read_unlock(), and synchronize_rcu() fences have
879 other properties which we discuss later. 831 other properties which we discuss later.
880 832
881 833
882 PROPAGATION ORDER RELATION: cumul-fence 834 PROPAGATION ORDER RELATION: cumul-fence
883 --------------------------------------- 835 ---------------------------------------
884 836
885 The fences which affect propagation order (i.e 837 The fences which affect propagation order (i.e., strong, release, and
886 smp_wmb() fences) are collectively referred to 838 smp_wmb() fences) are collectively referred to as cumul-fences, even
887 though smp_wmb() isn't A-cumulative. The cumu 839 though smp_wmb() isn't A-cumulative. The cumul-fence relation is
888 defined to link memory access events E and F w 840 defined to link memory access events E and F whenever:
889 841
890 E and F are both stores on the same CP 842 E and F are both stores on the same CPU and an smp_wmb() fence
891 event occurs between them in program o 843 event occurs between them in program order; or
892 844
893 F is a release fence and some X comes 845 F is a release fence and some X comes before F in program order,
894 where either X = E or else E ->rf X; o 846 where either X = E or else E ->rf X; or
895 847
896 A strong fence event occurs between so 848 A strong fence event occurs between some X and F in program
897 order, where either X = E or else E -> 849 order, where either X = E or else E ->rf X.
898 850
899 The operational model requires that whenever W 851 The operational model requires that whenever W and W' are both stores
900 and W ->cumul-fence W', then W must propagate 852 and W ->cumul-fence W', then W must propagate to any given CPU
901 before W' does. However, for different CPUs C 853 before W' does. However, for different CPUs C and C', it does not
902 require W to propagate to C before W' propagat 854 require W to propagate to C before W' propagates to C'.
903 855
904 856
905 DERIVATION OF THE LKMM FROM THE OPERATIONAL MO 857 DERIVATION OF THE LKMM FROM THE OPERATIONAL MODEL
906 ---------------------------------------------- 858 -------------------------------------------------
907 859
908 The LKMM is derived from the restrictions impo 860 The LKMM is derived from the restrictions imposed by the design
909 outlined above. These restrictions involve th 861 outlined above. These restrictions involve the necessity of
910 maintaining cache coherence and the fact that 862 maintaining cache coherence and the fact that a CPU can't operate on a
911 value before it knows what that value is, amon 863 value before it knows what that value is, among other things.
912 864
913 The formal version of the LKMM is defined by s !! 865 The formal version of the LKMM is defined by five requirements, or
914 axioms: 866 axioms:
915 867
916 Sequential consistency per variable: T 868 Sequential consistency per variable: This requires that the
917 system obey the four coherency rules. 869 system obey the four coherency rules.
918 870
919 Atomicity: This requires that atomic r 871 Atomicity: This requires that atomic read-modify-write
920 operations really are atomic, that is, 872 operations really are atomic, that is, no other stores can
921 sneak into the middle of such an updat 873 sneak into the middle of such an update.
922 874
923 Happens-before: This requires that cer 875 Happens-before: This requires that certain instructions are
924 executed in a specific order. 876 executed in a specific order.
925 877
926 Propagation: This requires that certai 878 Propagation: This requires that certain stores propagate to
927 CPUs and to RAM in a specific order. 879 CPUs and to RAM in a specific order.
928 880
929 Rcu: This requires that RCU read-side 881 Rcu: This requires that RCU read-side critical sections and
930 grace periods obey the rules of RCU, i 882 grace periods obey the rules of RCU, in particular, the
931 Grace-Period Guarantee. 883 Grace-Period Guarantee.
932 884
933 Plain-coherence: This requires that pl <<
934 (those not using READ_ONCE(), WRITE_ON <<
935 the operational model's rules regardin <<
936 <<
937 The first and second are quite common; they ca 885 The first and second are quite common; they can be found in many
938 memory models (such as those for C11/C++11). 886 memory models (such as those for C11/C++11). The "happens-before" and
939 "propagation" axioms have analogs in other mem 887 "propagation" axioms have analogs in other memory models as well. The
940 "rcu" and "plain-coherence" axioms are specifi !! 888 "rcu" axiom is specific to the LKMM.
941 889
942 Each of these axioms is discussed below. 890 Each of these axioms is discussed below.
943 891
944 892
945 SEQUENTIAL CONSISTENCY PER VARIABLE 893 SEQUENTIAL CONSISTENCY PER VARIABLE
946 ----------------------------------- 894 -----------------------------------
947 895
948 According to the principle of cache coherence, 896 According to the principle of cache coherence, the stores to any fixed
949 shared location in memory form a global orderi 897 shared location in memory form a global ordering. We can imagine
950 inserting the loads from that location into th 898 inserting the loads from that location into this ordering, by placing
951 each load between the store that it reads from 899 each load between the store that it reads from and the following
952 store. This leaves the relative positions of 900 store. This leaves the relative positions of loads that read from the
953 same store unspecified; let's say they are ins 901 same store unspecified; let's say they are inserted in program order,
954 first for CPU 0, then CPU 1, etc. 902 first for CPU 0, then CPU 1, etc.
955 903
956 You can check that the four coherency rules im 904 You can check that the four coherency rules imply that the rf, co, fr,
957 and po-loc relations agree with this global or 905 and po-loc relations agree with this global ordering; in other words,
958 whenever we have X ->rf Y or X ->co Y or X ->f 906 whenever we have X ->rf Y or X ->co Y or X ->fr Y or X ->po-loc Y, the
959 X event comes before the Y event in the global 907 X event comes before the Y event in the global ordering. The LKMM's
960 "coherence" axiom expresses this by requiring 908 "coherence" axiom expresses this by requiring the union of these
961 relations not to have any cycles. This means 909 relations not to have any cycles. This means it must not be possible
962 to find events 910 to find events
963 911
964 X0 -> X1 -> X2 -> ... -> Xn -> X0, 912 X0 -> X1 -> X2 -> ... -> Xn -> X0,
965 913
966 where each of the links is either rf, co, fr, 914 where each of the links is either rf, co, fr, or po-loc. This has to
967 hold if the accesses to the fixed memory locat 915 hold if the accesses to the fixed memory location can be ordered as
968 cache coherence demands. 916 cache coherence demands.
969 917
970 Although it is not obvious, it can be shown th 918 Although it is not obvious, it can be shown that the converse is also
971 true: This LKMM axiom implies that the four co 919 true: This LKMM axiom implies that the four coherency rules are
972 obeyed. 920 obeyed.
973 921
974 922
975 ATOMIC UPDATES: rmw 923 ATOMIC UPDATES: rmw
976 ------------------- 924 -------------------
977 925
978 What does it mean to say that a read-modify-wr 926 What does it mean to say that a read-modify-write (rmw) update, such
979 as atomic_inc(&x), is atomic? It means that t 927 as atomic_inc(&x), is atomic? It means that the memory location (x in
980 this case) does not get altered between the re 928 this case) does not get altered between the read and the write events
981 making up the atomic operation. In particular 929 making up the atomic operation. In particular, if two CPUs perform
982 atomic_inc(&x) concurrently, it must be guaran 930 atomic_inc(&x) concurrently, it must be guaranteed that the final
983 value of x will be the initial value plus two. 931 value of x will be the initial value plus two. We should never have
984 the following sequence of events: 932 the following sequence of events:
985 933
986 CPU 0 loads x obtaining 13; 934 CPU 0 loads x obtaining 13;
987 CPU 1 935 CPU 1 loads x obtaining 13;
988 CPU 0 stores 14 to x; 936 CPU 0 stores 14 to x;
989 CPU 1 937 CPU 1 stores 14 to x;
990 938
991 where the final value of x is wrong (14 rather 939 where the final value of x is wrong (14 rather than 15).
992 940
993 In this example, CPU 0's increment effectively 941 In this example, CPU 0's increment effectively gets lost because it
994 occurs in between CPU 1's load and store. To 942 occurs in between CPU 1's load and store. To put it another way, the
995 problem is that the position of CPU 0's store 943 problem is that the position of CPU 0's store in x's coherence order
996 is between the store that CPU 1 reads from and 944 is between the store that CPU 1 reads from and the store that CPU 1
997 performs. 945 performs.
998 946
999 The same analysis applies to all atomic update 947 The same analysis applies to all atomic update operations. Therefore,
1000 to enforce atomicity the LKMM requires that a 948 to enforce atomicity the LKMM requires that atomic updates follow this
1001 rule: Whenever R and W are the read and write 949 rule: Whenever R and W are the read and write events composing an
1002 atomic read-modify-write and W' is the write 950 atomic read-modify-write and W' is the write event which R reads from,
1003 there must not be any stores coming between W 951 there must not be any stores coming between W' and W in the coherence
1004 order. Equivalently, 952 order. Equivalently,
1005 953
1006 (R ->rmw W) implies (there is no X wi 954 (R ->rmw W) implies (there is no X with R ->fr X and X ->co W),
1007 955
1008 where the rmw relation links the read and wri 956 where the rmw relation links the read and write events making up each
1009 atomic update. This is what the LKMM's "atom 957 atomic update. This is what the LKMM's "atomic" axiom says.
1010 958
1011 Atomic rmw updates play one more role in the <<
1012 sequences". An rmw sequence is simply a bunc <<
1013 each update reads from the previous one. Wri <<
1014 looks like this: <<
1015 <<
1016 Z0 ->rf Y1 ->rmw Z1 ->rf ... ->rf Yn <<
1017 <<
1018 where Z0 is some store event and n can be any <<
1019 degenerate case). We write this relation as: <<
1020 Note that this implies Z0 and Zn are stores t <<
1021 <<
1022 Rmw sequences have a special property in the <<
1023 cumul-fence relation. That is, if we have: <<
1024 <<
1025 U ->cumul-fence X -> rmw-sequence Y <<
1026 <<
1027 then also U ->cumul-fence Y. Thinking about <<
1028 operational model, U ->cumul-fence X says tha <<
1029 to each CPU before the store X does. Then th <<
1030 linked by an rmw sequence means that U also p <<
1031 before Y does. In an analogous way, rmw sequ <<
1032 the w-post-bounded relation defined below in <<
1033 DATA RACES section. <<
1034 <<
1035 (The notion of rmw sequences in the LKMM is s <<
1036 the same as, that of release sequences in the <<
1037 were added to the LKMM to fix an obscure bug; <<
1038 updates with full-barrier semantics did not a <<
1039 at least as strong as atomic updates with rel <<
1040 <<
1041 959
1042 THE PRESERVED PROGRAM ORDER RELATION: ppo 960 THE PRESERVED PROGRAM ORDER RELATION: ppo
1043 ----------------------------------------- 961 -----------------------------------------
1044 962
1045 There are many situations where a CPU is obli !! 963 There are many situations where a CPU is obligated to execute two
1046 instructions in program order. We amalgamate 964 instructions in program order. We amalgamate them into the ppo (for
1047 "preserved program order") relation, which li 965 "preserved program order") relation, which links the po-earlier
1048 instruction to the po-later instruction and i 966 instruction to the po-later instruction and is thus a sub-relation of
1049 po. 967 po.
1050 968
1051 The operational model already includes a desc 969 The operational model already includes a description of one such
1052 situation: Fences are a source of ppo links. 970 situation: Fences are a source of ppo links. Suppose X and Y are
1053 memory accesses with X ->po Y; then the CPU m 971 memory accesses with X ->po Y; then the CPU must execute X before Y if
1054 any of the following hold: 972 any of the following hold:
1055 973
1056 A strong (smp_mb() or synchronize_rcu 974 A strong (smp_mb() or synchronize_rcu()) fence occurs between
1057 X and Y; 975 X and Y;
1058 976
1059 X and Y are both stores and an smp_wm 977 X and Y are both stores and an smp_wmb() fence occurs between
1060 them; 978 them;
1061 979
1062 X and Y are both loads and an smp_rmb 980 X and Y are both loads and an smp_rmb() fence occurs between
1063 them; 981 them;
1064 982
1065 X is also an acquire fence, such as s 983 X is also an acquire fence, such as smp_load_acquire();
1066 984
1067 Y is also a release fence, such as sm 985 Y is also a release fence, such as smp_store_release().
1068 986
1069 Another possibility, not mentioned earlier bu 987 Another possibility, not mentioned earlier but discussed in the next
1070 section, is: 988 section, is:
1071 989
1072 X and Y are both loads, X ->addr Y (i 990 X and Y are both loads, X ->addr Y (i.e., there is an address
1073 dependency from X to Y), and X is a R 991 dependency from X to Y), and X is a READ_ONCE() or an atomic
1074 access. 992 access.
1075 993
1076 Dependencies can also cause instructions to b 994 Dependencies can also cause instructions to be executed in program
1077 order. This is uncontroversial when the seco 995 order. This is uncontroversial when the second instruction is a
1078 store; either a data, address, or control dep 996 store; either a data, address, or control dependency from a load R to
1079 a store W will force the CPU to execute R bef 997 a store W will force the CPU to execute R before W. This is very
1080 simply because the CPU cannot tell the memory 998 simply because the CPU cannot tell the memory subsystem about W's
1081 store before it knows what value should be st 999 store before it knows what value should be stored (in the case of a
1082 data dependency), what location it should be 1000 data dependency), what location it should be stored into (in the case
1083 of an address dependency), or whether the sto 1001 of an address dependency), or whether the store should actually take
1084 place (in the case of a control dependency). 1002 place (in the case of a control dependency).
1085 1003
1086 Dependencies to load instructions are more pr 1004 Dependencies to load instructions are more problematic. To begin with,
1087 there is no such thing as a data dependency t 1005 there is no such thing as a data dependency to a load. Next, a CPU
1088 has no reason to respect a control dependency 1006 has no reason to respect a control dependency to a load, because it
1089 can always satisfy the second load speculativ 1007 can always satisfy the second load speculatively before the first, and
1090 then ignore the result if it turns out that t 1008 then ignore the result if it turns out that the second load shouldn't
1091 be executed after all. And lastly, the real 1009 be executed after all. And lastly, the real difficulties begin when
1092 we consider address dependencies to loads. 1010 we consider address dependencies to loads.
1093 1011
1094 To be fair about it, all Linux-supported arch 1012 To be fair about it, all Linux-supported architectures do execute
1095 loads in program order if there is an address 1013 loads in program order if there is an address dependency between them.
1096 After all, a CPU cannot ask the memory subsys 1014 After all, a CPU cannot ask the memory subsystem to load a value from
1097 a particular location before it knows what th 1015 a particular location before it knows what that location is. However,
1098 the split-cache design used by Alpha can caus 1016 the split-cache design used by Alpha can cause it to behave in a way
1099 that looks as if the loads were executed out 1017 that looks as if the loads were executed out of order (see the next
1100 section for more details). The kernel includ 1018 section for more details). The kernel includes a workaround for this
1101 problem when the loads come from READ_ONCE(), 1019 problem when the loads come from READ_ONCE(), and therefore the LKMM
1102 includes address dependencies to loads in the 1020 includes address dependencies to loads in the ppo relation.
1103 1021
1104 On the other hand, dependencies can indirectl 1022 On the other hand, dependencies can indirectly affect the ordering of
1105 two loads. This happens when there is a depe 1023 two loads. This happens when there is a dependency from a load to a
1106 store and a second, po-later load reads from 1024 store and a second, po-later load reads from that store:
1107 1025
1108 R ->dep W ->rfi R', 1026 R ->dep W ->rfi R',
1109 1027
1110 where the dep link can be either an address o 1028 where the dep link can be either an address or a data dependency. In
1111 this situation we know it is possible for the 1029 this situation we know it is possible for the CPU to execute R' before
1112 W, because it can forward the value that W wi 1030 W, because it can forward the value that W will store to R'. But it
1113 cannot execute R' before R, because it cannot 1031 cannot execute R' before R, because it cannot forward the value before
1114 it knows what that value is, or that W and R' 1032 it knows what that value is, or that W and R' do access the same
1115 location. However, if there is merely a cont 1033 location. However, if there is merely a control dependency between R
1116 and W then the CPU can speculatively forward 1034 and W then the CPU can speculatively forward W to R' before executing
1117 R; if the speculation turns out to be wrong t 1035 R; if the speculation turns out to be wrong then the CPU merely has to
1118 restart or abandon R'. 1036 restart or abandon R'.
1119 1037
1120 (In theory, a CPU might forward a store to a 1038 (In theory, a CPU might forward a store to a load when it runs across
1121 an address dependency like this: 1039 an address dependency like this:
1122 1040
1123 r1 = READ_ONCE(ptr); 1041 r1 = READ_ONCE(ptr);
1124 WRITE_ONCE(*r1, 17); 1042 WRITE_ONCE(*r1, 17);
1125 r2 = READ_ONCE(*r1); 1043 r2 = READ_ONCE(*r1);
1126 1044
1127 because it could tell that the store and the 1045 because it could tell that the store and the second load access the
1128 same location even before it knows what the l 1046 same location even before it knows what the location's address is.
1129 However, none of the architectures supported 1047 However, none of the architectures supported by the Linux kernel do
1130 this.) 1048 this.)
1131 1049
1132 Two memory accesses of the same location must 1050 Two memory accesses of the same location must always be executed in
1133 program order if the second access is a store 1051 program order if the second access is a store. Thus, if we have
1134 1052
1135 R ->po-loc W 1053 R ->po-loc W
1136 1054
1137 (the po-loc link says that R comes before W i 1055 (the po-loc link says that R comes before W in program order and they
1138 access the same location), the CPU is obliged 1056 access the same location), the CPU is obliged to execute W after R.
1139 If it executed W first then the memory subsys 1057 If it executed W first then the memory subsystem would respond to R's
1140 read request with the value stored by W (or a 1058 read request with the value stored by W (or an even later store), in
1141 violation of the read-write coherence rule. 1059 violation of the read-write coherence rule. Similarly, if we had
1142 1060
1143 W ->po-loc W' 1061 W ->po-loc W'
1144 1062
1145 and the CPU executed W' before W, then the me 1063 and the CPU executed W' before W, then the memory subsystem would put
1146 W' before W in the coherence order. It would 1064 W' before W in the coherence order. It would effectively cause W to
1147 overwrite W', in violation of the write-write 1065 overwrite W', in violation of the write-write coherence rule.
1148 (Interestingly, an early ARMv8 memory model, 1066 (Interestingly, an early ARMv8 memory model, now obsolete, proposed
1149 allowing out-of-order writes like this to occ 1067 allowing out-of-order writes like this to occur. The model avoided
1150 violating the write-write coherence rule by r 1068 violating the write-write coherence rule by requiring the CPU not to
1151 send the W write to the memory subsystem at a 1069 send the W write to the memory subsystem at all!)
1152 1070
1153 1071
1154 AND THEN THERE WAS ALPHA 1072 AND THEN THERE WAS ALPHA
1155 ------------------------ 1073 ------------------------
1156 1074
1157 As mentioned above, the Alpha architecture is 1075 As mentioned above, the Alpha architecture is unique in that it does
1158 not appear to respect address dependencies to 1076 not appear to respect address dependencies to loads. This means that
1159 code such as the following: 1077 code such as the following:
1160 1078
1161 int x = 0; 1079 int x = 0;
1162 int y = -1; 1080 int y = -1;
1163 int *ptr = &y; 1081 int *ptr = &y;
1164 1082
1165 P0() 1083 P0()
1166 { 1084 {
1167 WRITE_ONCE(x, 1); 1085 WRITE_ONCE(x, 1);
1168 smp_wmb(); 1086 smp_wmb();
1169 WRITE_ONCE(ptr, &x); 1087 WRITE_ONCE(ptr, &x);
1170 } 1088 }
1171 1089
1172 P1() 1090 P1()
1173 { 1091 {
1174 int *r1; 1092 int *r1;
1175 int r2; 1093 int r2;
1176 1094
1177 r1 = ptr; 1095 r1 = ptr;
1178 r2 = READ_ONCE(*r1); 1096 r2 = READ_ONCE(*r1);
1179 } 1097 }
1180 1098
1181 can malfunction on Alpha systems (notice that 1099 can malfunction on Alpha systems (notice that P1 uses an ordinary load
1182 to read ptr instead of READ_ONCE()). It is q 1100 to read ptr instead of READ_ONCE()). It is quite possible that r1 = &x
1183 and r2 = 0 at the end, in spite of the addres 1101 and r2 = 0 at the end, in spite of the address dependency.
1184 1102
1185 At first glance this doesn't seem to make sen 1103 At first glance this doesn't seem to make sense. We know that the
1186 smp_wmb() forces P0's store to x to propagate 1104 smp_wmb() forces P0's store to x to propagate to P1 before the store
1187 to ptr does. And since P1 can't execute its 1105 to ptr does. And since P1 can't execute its second load
1188 until it knows what location to load from, i. 1106 until it knows what location to load from, i.e., after executing its
1189 first load, the value x = 1 must have propaga 1107 first load, the value x = 1 must have propagated to P1 before the
1190 second load executed. So why doesn't r2 end 1108 second load executed. So why doesn't r2 end up equal to 1?
1191 1109
1192 The answer lies in the Alpha's split local ca 1110 The answer lies in the Alpha's split local caches. Although the two
1193 stores do reach P1's local cache in the prope 1111 stores do reach P1's local cache in the proper order, it can happen
1194 that the first store is processed by a busy p 1112 that the first store is processed by a busy part of the cache while
1195 the second store is processed by an idle part 1113 the second store is processed by an idle part. As a result, the x = 1
1196 value may not become available for P1's CPU t 1114 value may not become available for P1's CPU to read until after the
1197 ptr = &x value does, leading to the undesirab 1115 ptr = &x value does, leading to the undesirable result above. The
1198 final effect is that even though the two load 1116 final effect is that even though the two loads really are executed in
1199 program order, it appears that they aren't. 1117 program order, it appears that they aren't.
1200 1118
1201 This could not have happened if the local cac 1119 This could not have happened if the local cache had processed the
1202 incoming stores in FIFO order. By contrast, 1120 incoming stores in FIFO order. By contrast, other architectures
1203 maintain at least the appearance of FIFO orde 1121 maintain at least the appearance of FIFO order.
1204 1122
1205 In practice, this difficulty is solved by ins 1123 In practice, this difficulty is solved by inserting a special fence
1206 between P1's two loads when the kernel is com 1124 between P1's two loads when the kernel is compiled for the Alpha
1207 architecture. In fact, as of version 4.15, t 1125 architecture. In fact, as of version 4.15, the kernel automatically
1208 adds this fence after every READ_ONCE() and a !! 1126 adds this fence (called smp_read_barrier_depends() and defined as
1209 effect of the fence is to cause the CPU not t !! 1127 nothing at all on non-Alpha builds) after every READ_ONCE() and atomic
1210 instructions until after the local cache has !! 1128 load. The effect of the fence is to cause the CPU not to execute any
1211 the stores it has already received. Thus, if !! 1129 po-later instructions until after the local cache has finished
>> 1130 processing all the stores it has already received. Thus, if the code
>> 1131 was changed to:
1212 1132
1213 P1() 1133 P1()
1214 { 1134 {
1215 int *r1; 1135 int *r1;
1216 int r2; 1136 int r2;
1217 1137
1218 r1 = READ_ONCE(ptr); 1138 r1 = READ_ONCE(ptr);
1219 r2 = READ_ONCE(*r1); 1139 r2 = READ_ONCE(*r1);
1220 } 1140 }
1221 1141
1222 then we would never get r1 = &x and r2 = 0. 1142 then we would never get r1 = &x and r2 = 0. By the time P1 executed
1223 its second load, the x = 1 store would alread 1143 its second load, the x = 1 store would already be fully processed by
1224 the local cache and available for satisfying 1144 the local cache and available for satisfying the read request. Thus
1225 we have yet another reason why shared data sh 1145 we have yet another reason why shared data should always be read with
1226 READ_ONCE() or another synchronization primit 1146 READ_ONCE() or another synchronization primitive rather than accessed
1227 directly. 1147 directly.
1228 1148
1229 The LKMM requires that smp_rmb(), acquire fen 1149 The LKMM requires that smp_rmb(), acquire fences, and strong fences
1230 share this property: They do not allow the CP !! 1150 share this property with smp_read_barrier_depends(): They do not allow
1231 instructions (or po-later loads in the case o !! 1151 the CPU to execute any po-later instructions (or po-later loads in the
1232 outstanding stores have been processed by the !! 1152 case of smp_rmb()) until all outstanding stores have been processed by
1233 case of a strong fence, the CPU first has to !! 1153 the local cache. In the case of a strong fence, the CPU first has to
1234 po-earlier stores to propagate to every other !! 1154 wait for all of its po-earlier stores to propagate to every other CPU
1235 it has to wait for the local cache to process !! 1155 in the system; then it has to wait for the local cache to process all
1236 as of that time -- not just the stores receiv !! 1156 the stores received as of that time -- not just the stores received
1237 began. !! 1157 when the strong fence began.
1238 1158
1239 And of course, none of this matters for any a 1159 And of course, none of this matters for any architecture other than
1240 Alpha. 1160 Alpha.
1241 1161
1242 1162
1243 THE HAPPENS-BEFORE RELATION: hb 1163 THE HAPPENS-BEFORE RELATION: hb
1244 ------------------------------- 1164 -------------------------------
1245 1165
1246 The happens-before relation (hb) links memory 1166 The happens-before relation (hb) links memory accesses that have to
1247 execute in a certain order. hb includes the 1167 execute in a certain order. hb includes the ppo relation and two
1248 others, one of which is rfe. 1168 others, one of which is rfe.
1249 1169
1250 W ->rfe R implies that W and R are on differe 1170 W ->rfe R implies that W and R are on different CPUs. It also means
1251 that W's store must have propagated to R's CP 1171 that W's store must have propagated to R's CPU before R executed;
1252 otherwise R could not have read the value sto 1172 otherwise R could not have read the value stored by W. Therefore W
1253 must have executed before R, and so we have W 1173 must have executed before R, and so we have W ->hb R.
1254 1174
1255 The equivalent fact need not hold if W ->rfi 1175 The equivalent fact need not hold if W ->rfi R (i.e., W and R are on
1256 the same CPU). As we have already seen, the 1176 the same CPU). As we have already seen, the operational model allows
1257 W's value to be forwarded to R in such cases, 1177 W's value to be forwarded to R in such cases, meaning that R may well
1258 execute before W does. 1178 execute before W does.
1259 1179
1260 It's important to understand that neither coe 1180 It's important to understand that neither coe nor fre is included in
1261 hb, despite their similarities to rfe. For e 1181 hb, despite their similarities to rfe. For example, suppose we have
1262 W ->coe W'. This means that W and W' are sto 1182 W ->coe W'. This means that W and W' are stores to the same location,
1263 they execute on different CPUs, and W comes b 1183 they execute on different CPUs, and W comes before W' in the coherence
1264 order (i.e., W' overwrites W). Nevertheless, 1184 order (i.e., W' overwrites W). Nevertheless, it is possible for W' to
1265 execute before W, because the decision as to 1185 execute before W, because the decision as to which store overwrites
1266 the other is made later by the memory subsyst 1186 the other is made later by the memory subsystem. When the stores are
1267 nearly simultaneous, either one can come out 1187 nearly simultaneous, either one can come out on top. Similarly,
1268 R ->fre W means that W overwrites the value w 1188 R ->fre W means that W overwrites the value which R reads, but it
1269 doesn't mean that W has to execute after R. 1189 doesn't mean that W has to execute after R. All that's necessary is
1270 for the memory subsystem not to propagate W t 1190 for the memory subsystem not to propagate W to R's CPU until after R
1271 has executed, which is possible if W executes 1191 has executed, which is possible if W executes shortly before R.
1272 1192
1273 The third relation included in hb is like ppo 1193 The third relation included in hb is like ppo, in that it only links
1274 events that are on the same CPU. However it 1194 events that are on the same CPU. However it is more difficult to
1275 explain, because it arises only indirectly fr 1195 explain, because it arises only indirectly from the requirement of
1276 cache coherence. The relation is called prop 1196 cache coherence. The relation is called prop, and it links two events
1277 on CPU C in situations where a store from som 1197 on CPU C in situations where a store from some other CPU comes after
1278 the first event in the coherence order and pr 1198 the first event in the coherence order and propagates to C before the
1279 second event executes. 1199 second event executes.
1280 1200
1281 This is best explained with some examples. T 1201 This is best explained with some examples. The simplest case looks
1282 like this: 1202 like this:
1283 1203
1284 int x; 1204 int x;
1285 1205
1286 P0() 1206 P0()
1287 { 1207 {
1288 int r1; 1208 int r1;
1289 1209
1290 WRITE_ONCE(x, 1); 1210 WRITE_ONCE(x, 1);
1291 r1 = READ_ONCE(x); 1211 r1 = READ_ONCE(x);
1292 } 1212 }
1293 1213
1294 P1() 1214 P1()
1295 { 1215 {
1296 WRITE_ONCE(x, 8); 1216 WRITE_ONCE(x, 8);
1297 } 1217 }
1298 1218
1299 If r1 = 8 at the end then P0's accesses must 1219 If r1 = 8 at the end then P0's accesses must have executed in program
1300 order. We can deduce this from the operation 1220 order. We can deduce this from the operational model; if P0's load
1301 had executed before its store then the value 1221 had executed before its store then the value of the store would have
1302 been forwarded to the load, so r1 would have 1222 been forwarded to the load, so r1 would have ended up equal to 1, not
1303 8. In this case there is a prop link from P0 1223 8. In this case there is a prop link from P0's write event to its read
1304 event, because P1's store came after P0's sto 1224 event, because P1's store came after P0's store in x's coherence
1305 order, and P1's store propagated to P0 before 1225 order, and P1's store propagated to P0 before P0's load executed.
1306 1226
1307 An equally simple case involves two loads of 1227 An equally simple case involves two loads of the same location that
1308 read from different stores: 1228 read from different stores:
1309 1229
1310 int x = 0; 1230 int x = 0;
1311 1231
1312 P0() 1232 P0()
1313 { 1233 {
1314 int r1, r2; 1234 int r1, r2;
1315 1235
1316 r1 = READ_ONCE(x); 1236 r1 = READ_ONCE(x);
1317 r2 = READ_ONCE(x); 1237 r2 = READ_ONCE(x);
1318 } 1238 }
1319 1239
1320 P1() 1240 P1()
1321 { 1241 {
1322 WRITE_ONCE(x, 9); 1242 WRITE_ONCE(x, 9);
1323 } 1243 }
1324 1244
1325 If r1 = 0 and r2 = 9 at the end then P0's acc 1245 If r1 = 0 and r2 = 9 at the end then P0's accesses must have executed
1326 in program order. If the second load had exe 1246 in program order. If the second load had executed before the first
1327 then the x = 9 store must have been propagate 1247 then the x = 9 store must have been propagated to P0 before the first
1328 load executed, and so r1 would have been 9 ra 1248 load executed, and so r1 would have been 9 rather than 0. In this
1329 case there is a prop link from P0's first rea 1249 case there is a prop link from P0's first read event to its second,
1330 because P1's store overwrote the value read b 1250 because P1's store overwrote the value read by P0's first load, and
1331 P1's store propagated to P0 before P0's secon 1251 P1's store propagated to P0 before P0's second load executed.
1332 1252
1333 Less trivial examples of prop all involve fen 1253 Less trivial examples of prop all involve fences. Unlike the simple
1334 examples above, they can require that some in 1254 examples above, they can require that some instructions are executed
1335 out of program order. This next one should l 1255 out of program order. This next one should look familiar:
1336 1256
1337 int buf = 0, flag = 0; 1257 int buf = 0, flag = 0;
1338 1258
1339 P0() 1259 P0()
1340 { 1260 {
1341 WRITE_ONCE(buf, 1); 1261 WRITE_ONCE(buf, 1);
1342 smp_wmb(); 1262 smp_wmb();
1343 WRITE_ONCE(flag, 1); 1263 WRITE_ONCE(flag, 1);
1344 } 1264 }
1345 1265
1346 P1() 1266 P1()
1347 { 1267 {
1348 int r1; 1268 int r1;
1349 int r2; 1269 int r2;
1350 1270
1351 r1 = READ_ONCE(flag); 1271 r1 = READ_ONCE(flag);
1352 r2 = READ_ONCE(buf); 1272 r2 = READ_ONCE(buf);
1353 } 1273 }
1354 1274
1355 This is the MP pattern again, with an smp_wmb 1275 This is the MP pattern again, with an smp_wmb() fence between the two
1356 stores. If r1 = 1 and r2 = 0 at the end then 1276 stores. If r1 = 1 and r2 = 0 at the end then there is a prop link
1357 from P1's second load to its first (backwards 1277 from P1's second load to its first (backwards!). The reason is
1358 similar to the previous examples: The value P 1278 similar to the previous examples: The value P1 loads from buf gets
1359 overwritten by P0's store to buf, the fence g 1279 overwritten by P0's store to buf, the fence guarantees that the store
1360 to buf will propagate to P1 before the store 1280 to buf will propagate to P1 before the store to flag does, and the
1361 store to flag propagates to P1 before P1 read 1281 store to flag propagates to P1 before P1 reads flag.
1362 1282
1363 The prop link says that in order to obtain th 1283 The prop link says that in order to obtain the r1 = 1, r2 = 0 result,
1364 P1 must execute its second load before the fi 1284 P1 must execute its second load before the first. Indeed, if the load
1365 from flag were executed first, then the buf = 1285 from flag were executed first, then the buf = 1 store would already
1366 have propagated to P1 by the time P1's load f 1286 have propagated to P1 by the time P1's load from buf executed, so r2
1367 would have been 1 at the end, not 0. (The re 1287 would have been 1 at the end, not 0. (The reasoning holds even for
1368 Alpha, although the details are more complica 1288 Alpha, although the details are more complicated and we will not go
1369 into them.) 1289 into them.)
1370 1290
1371 But what if we put an smp_rmb() fence between 1291 But what if we put an smp_rmb() fence between P1's loads? The fence
1372 would force the two loads to be executed in p 1292 would force the two loads to be executed in program order, and it
1373 would generate a cycle in the hb relation: Th 1293 would generate a cycle in the hb relation: The fence would create a ppo
1374 link (hence an hb link) from the first load t 1294 link (hence an hb link) from the first load to the second, and the
1375 prop relation would give an hb link from the 1295 prop relation would give an hb link from the second load to the first.
1376 Since an instruction can't execute before its 1296 Since an instruction can't execute before itself, we are forced to
1377 conclude that if an smp_rmb() fence is added, 1297 conclude that if an smp_rmb() fence is added, the r1 = 1, r2 = 0
1378 outcome is impossible -- as it should be. 1298 outcome is impossible -- as it should be.
1379 1299
1380 The formal definition of the prop relation in 1300 The formal definition of the prop relation involves a coe or fre link,
1381 followed by an arbitrary number of cumul-fenc 1301 followed by an arbitrary number of cumul-fence links, ending with an
1382 rfe link. You can concoct more exotic exampl 1302 rfe link. You can concoct more exotic examples, containing more than
1383 one fence, although this quickly leads to dim 1303 one fence, although this quickly leads to diminishing returns in terms
1384 of complexity. For instance, here's an examp 1304 of complexity. For instance, here's an example containing a coe link
1385 followed by two cumul-fences and an rfe link, !! 1305 followed by two fences and an rfe link, utilizing the fact that
1386 release fences are A-cumulative: 1306 release fences are A-cumulative:
1387 1307
1388 int x, y, z; 1308 int x, y, z;
1389 1309
1390 P0() 1310 P0()
1391 { 1311 {
1392 int r0; 1312 int r0;
1393 1313
1394 WRITE_ONCE(x, 1); 1314 WRITE_ONCE(x, 1);
1395 r0 = READ_ONCE(z); 1315 r0 = READ_ONCE(z);
1396 } 1316 }
1397 1317
1398 P1() 1318 P1()
1399 { 1319 {
1400 WRITE_ONCE(x, 2); 1320 WRITE_ONCE(x, 2);
1401 smp_wmb(); 1321 smp_wmb();
1402 WRITE_ONCE(y, 1); 1322 WRITE_ONCE(y, 1);
1403 } 1323 }
1404 1324
1405 P2() 1325 P2()
1406 { 1326 {
1407 int r2; 1327 int r2;
1408 1328
1409 r2 = READ_ONCE(y); 1329 r2 = READ_ONCE(y);
1410 smp_store_release(&z, 1); 1330 smp_store_release(&z, 1);
1411 } 1331 }
1412 1332
1413 If x = 2, r0 = 1, and r2 = 1 after this code 1333 If x = 2, r0 = 1, and r2 = 1 after this code runs then there is a prop
1414 link from P0's store to its load. This is be 1334 link from P0's store to its load. This is because P0's store gets
1415 overwritten by P1's store since x = 2 at the 1335 overwritten by P1's store since x = 2 at the end (a coe link), the
1416 smp_wmb() ensures that P1's store to x propag 1336 smp_wmb() ensures that P1's store to x propagates to P2 before the
1417 store to y does (the first cumul-fence), the !! 1337 store to y does (the first fence), the store to y propagates to P2
1418 before P2's load and store execute, P2's smp_ 1338 before P2's load and store execute, P2's smp_store_release()
1419 guarantees that the stores to x and y both pr 1339 guarantees that the stores to x and y both propagate to P0 before the
1420 store to z does (the second cumul-fence), and !! 1340 store to z does (the second fence), and P0's load executes after the
1421 store to z has propagated to P0 (an rfe link) 1341 store to z has propagated to P0 (an rfe link).
1422 1342
1423 In summary, the fact that the hb relation lin 1343 In summary, the fact that the hb relation links memory access events
1424 in the order they execute means that it must 1344 in the order they execute means that it must not have cycles. This
1425 requirement is the content of the LKMM's "hap 1345 requirement is the content of the LKMM's "happens-before" axiom.
1426 1346
1427 The LKMM defines yet another relation connect 1347 The LKMM defines yet another relation connected to times of
1428 instruction execution, but it is not included 1348 instruction execution, but it is not included in hb. It relies on the
1429 particular properties of strong fences, which 1349 particular properties of strong fences, which we cover in the next
1430 section. 1350 section.
1431 1351
1432 1352
1433 THE PROPAGATES-BEFORE RELATION: pb 1353 THE PROPAGATES-BEFORE RELATION: pb
1434 ---------------------------------- 1354 ----------------------------------
1435 1355
1436 The propagates-before (pb) relation capitaliz 1356 The propagates-before (pb) relation capitalizes on the special
1437 features of strong fences. It links two even 1357 features of strong fences. It links two events E and F whenever some
1438 store is coherence-later than E and propagate 1358 store is coherence-later than E and propagates to every CPU and to RAM
1439 before F executes. The formal definition req 1359 before F executes. The formal definition requires that E be linked to
1440 F via a coe or fre link, an arbitrary number 1360 F via a coe or fre link, an arbitrary number of cumul-fences, an
1441 optional rfe link, a strong fence, and an arb 1361 optional rfe link, a strong fence, and an arbitrary number of hb
1442 links. Let's see how this definition works o 1362 links. Let's see how this definition works out.
1443 1363
1444 Consider first the case where E is a store (i 1364 Consider first the case where E is a store (implying that the sequence
1445 of links begins with coe). Then there are ev 1365 of links begins with coe). Then there are events W, X, Y, and Z such
1446 that: 1366 that:
1447 1367
1448 E ->coe W ->cumul-fence* X ->rfe? Y - 1368 E ->coe W ->cumul-fence* X ->rfe? Y ->strong-fence Z ->hb* F,
1449 1369
1450 where the * suffix indicates an arbitrary num 1370 where the * suffix indicates an arbitrary number of links of the
1451 specified type, and the ? suffix indicates th 1371 specified type, and the ? suffix indicates the link is optional (Y may
1452 be equal to X). Because of the cumul-fence l 1372 be equal to X). Because of the cumul-fence links, we know that W will
1453 propagate to Y's CPU before X does, hence bef 1373 propagate to Y's CPU before X does, hence before Y executes and hence
1454 before the strong fence executes. Because th 1374 before the strong fence executes. Because this fence is strong, we
1455 know that W will propagate to every CPU and t 1375 know that W will propagate to every CPU and to RAM before Z executes.
1456 And because of the hb links, we know that Z w 1376 And because of the hb links, we know that Z will execute before F.
1457 Thus W, which comes later than E in the coher 1377 Thus W, which comes later than E in the coherence order, will
1458 propagate to every CPU and to RAM before F ex 1378 propagate to every CPU and to RAM before F executes.
1459 1379
1460 The case where E is a load is exactly the sam 1380 The case where E is a load is exactly the same, except that the first
1461 link in the sequence is fre instead of coe. 1381 link in the sequence is fre instead of coe.
1462 1382
1463 The existence of a pb link from E to F implie 1383 The existence of a pb link from E to F implies that E must execute
1464 before F. To see why, suppose that F execute 1384 before F. To see why, suppose that F executed first. Then W would
1465 have propagated to E's CPU before E executed. 1385 have propagated to E's CPU before E executed. If E was a store, the
1466 memory subsystem would then be forced to make 1386 memory subsystem would then be forced to make E come after W in the
1467 coherence order, contradicting the fact that 1387 coherence order, contradicting the fact that E ->coe W. If E was a
1468 load, the memory subsystem would then be forc 1388 load, the memory subsystem would then be forced to satisfy E's read
1469 request with the value stored by W or an even 1389 request with the value stored by W or an even later store,
1470 contradicting the fact that E ->fre W. 1390 contradicting the fact that E ->fre W.
1471 1391
1472 A good example illustrating how pb works is t 1392 A good example illustrating how pb works is the SB pattern with strong
1473 fences: 1393 fences:
1474 1394
1475 int x = 0, y = 0; 1395 int x = 0, y = 0;
1476 1396
1477 P0() 1397 P0()
1478 { 1398 {
1479 int r0; 1399 int r0;
1480 1400
1481 WRITE_ONCE(x, 1); 1401 WRITE_ONCE(x, 1);
1482 smp_mb(); 1402 smp_mb();
1483 r0 = READ_ONCE(y); 1403 r0 = READ_ONCE(y);
1484 } 1404 }
1485 1405
1486 P1() 1406 P1()
1487 { 1407 {
1488 int r1; 1408 int r1;
1489 1409
1490 WRITE_ONCE(y, 1); 1410 WRITE_ONCE(y, 1);
1491 smp_mb(); 1411 smp_mb();
1492 r1 = READ_ONCE(x); 1412 r1 = READ_ONCE(x);
1493 } 1413 }
1494 1414
1495 If r0 = 0 at the end then there is a pb link 1415 If r0 = 0 at the end then there is a pb link from P0's load to P1's
1496 load: an fre link from P0's load to P1's stor 1416 load: an fre link from P0's load to P1's store (which overwrites the
1497 value read by P0), and a strong fence between 1417 value read by P0), and a strong fence between P1's store and its load.
1498 In this example, the sequences of cumul-fence 1418 In this example, the sequences of cumul-fence and hb links are empty.
1499 Note that this pb link is not included in hb 1419 Note that this pb link is not included in hb as an instance of prop,
1500 because it does not start and end on the same 1420 because it does not start and end on the same CPU.
1501 1421
1502 Similarly, if r1 = 0 at the end then there is 1422 Similarly, if r1 = 0 at the end then there is a pb link from P1's load
1503 to P0's. This means that if both r1 and r2 w 1423 to P0's. This means that if both r1 and r2 were 0 there would be a
1504 cycle in pb, which is not possible since an i 1424 cycle in pb, which is not possible since an instruction cannot execute
1505 before itself. Thus, adding smp_mb() fences 1425 before itself. Thus, adding smp_mb() fences to the SB pattern
1506 prevents the r0 = 0, r1 = 0 outcome. 1426 prevents the r0 = 0, r1 = 0 outcome.
1507 1427
1508 In summary, the fact that the pb relation lin 1428 In summary, the fact that the pb relation links events in the order
1509 they execute means that it cannot have cycles 1429 they execute means that it cannot have cycles. This requirement is
1510 the content of the LKMM's "propagation" axiom 1430 the content of the LKMM's "propagation" axiom.
1511 1431
1512 1432
1513 RCU RELATIONS: rcu-link, rcu-gp, rcu-rscsi, r !! 1433 RCU RELATIONS: rcu-link, gp, rscs, rcu-fence, and rb
1514 --------------------------------------------- !! 1434 ----------------------------------------------------
1515 1435
1516 RCU (Read-Copy-Update) is a powerful synchron 1436 RCU (Read-Copy-Update) is a powerful synchronization mechanism. It
1517 rests on two concepts: grace periods and read 1437 rests on two concepts: grace periods and read-side critical sections.
1518 1438
1519 A grace period is the span of time occupied b 1439 A grace period is the span of time occupied by a call to
1520 synchronize_rcu(). A read-side critical sect 1440 synchronize_rcu(). A read-side critical section (or just critical
1521 section, for short) is a region of code delim 1441 section, for short) is a region of code delimited by rcu_read_lock()
1522 at the start and rcu_read_unlock() at the end 1442 at the start and rcu_read_unlock() at the end. Critical sections can
1523 be nested, although we won't make use of this 1443 be nested, although we won't make use of this fact.
1524 1444
1525 As far as memory models are concerned, RCU's 1445 As far as memory models are concerned, RCU's main feature is its
1526 Grace-Period Guarantee, which states that a c 1446 Grace-Period Guarantee, which states that a critical section can never
1527 span a full grace period. In more detail, th 1447 span a full grace period. In more detail, the Guarantee says:
1528 1448
1529 For any critical section C and any gr !! 1449 If a critical section starts before a grace period then it
1530 one of the following statements must !! 1450 must end before the grace period does. In addition, every
1531 !! 1451 store that propagates to the critical section's CPU before the
1532 (1) C ends before G does, and in addition !! 1452 end of the critical section must propagate to every CPU before
1533 propagates to C's CPU before the end !! 1453 the end of the grace period.
1534 every CPU before G ends. !! 1454
1535 !! 1455 If a critical section ends after a grace period ends then it
1536 (2) G starts before C does, and in additi !! 1456 must start after the grace period does. In addition, every
1537 propagates to G's CPU before the star !! 1457 store that propagates to the grace period's CPU before the
1538 to every CPU before C starts. !! 1458 start of the grace period must propagate to every CPU before
1539 !! 1459 the start of the critical section.
1540 In particular, it is not possible for a criti <<
1541 before and end after a grace period. <<
1542 1460
1543 Here is a simple example of RCU in action: 1461 Here is a simple example of RCU in action:
1544 1462
1545 int x, y; 1463 int x, y;
1546 1464
1547 P0() 1465 P0()
1548 { 1466 {
1549 rcu_read_lock(); 1467 rcu_read_lock();
1550 WRITE_ONCE(x, 1); 1468 WRITE_ONCE(x, 1);
1551 WRITE_ONCE(y, 1); 1469 WRITE_ONCE(y, 1);
1552 rcu_read_unlock(); 1470 rcu_read_unlock();
1553 } 1471 }
1554 1472
1555 P1() 1473 P1()
1556 { 1474 {
1557 int r1, r2; 1475 int r1, r2;
1558 1476
1559 r1 = READ_ONCE(x); 1477 r1 = READ_ONCE(x);
1560 synchronize_rcu(); 1478 synchronize_rcu();
1561 r2 = READ_ONCE(y); 1479 r2 = READ_ONCE(y);
1562 } 1480 }
1563 1481
1564 The Grace Period Guarantee tells us that when 1482 The Grace Period Guarantee tells us that when this code runs, it will
1565 never end with r1 = 1 and r2 = 0. The reason 1483 never end with r1 = 1 and r2 = 0. The reasoning is as follows. r1 = 1
1566 means that P0's store to x propagated to P1 b 1484 means that P0's store to x propagated to P1 before P1 called
1567 synchronize_rcu(), so P0's critical section m 1485 synchronize_rcu(), so P0's critical section must have started before
1568 P1's grace period, contrary to part (2) of th !! 1486 P1's grace period. On the other hand, r2 = 0 means that P0's store to
1569 other hand, r2 = 0 means that P0's store to y !! 1487 y, which occurs before the end of the critical section, did not
1570 end of the critical section, did not propagat !! 1488 propagate to P1 before the end of the grace period, violating the
1571 the grace period, contrary to part (1). Toge !! 1489 Guarantee.
1572 the Guarantee. <<
1573 1490
1574 In the kernel's implementations of RCU, the r 1491 In the kernel's implementations of RCU, the requirements for stores
1575 to propagate to every CPU are fulfilled by pl 1492 to propagate to every CPU are fulfilled by placing strong fences at
1576 suitable places in the RCU-related code. Thu 1493 suitable places in the RCU-related code. Thus, if a critical section
1577 starts before a grace period does then the cr 1494 starts before a grace period does then the critical section's CPU will
1578 execute an smp_mb() fence after the end of th 1495 execute an smp_mb() fence after the end of the critical section and
1579 some time before the grace period's synchroni 1496 some time before the grace period's synchronize_rcu() call returns.
1580 And if a critical section ends after a grace 1497 And if a critical section ends after a grace period does then the
1581 synchronize_rcu() routine will execute an smp 1498 synchronize_rcu() routine will execute an smp_mb() fence at its start
1582 and some time before the critical section's o 1499 and some time before the critical section's opening rcu_read_lock()
1583 executes. 1500 executes.
1584 1501
1585 What exactly do we mean by saying that a crit 1502 What exactly do we mean by saying that a critical section "starts
1586 before" or "ends after" a grace period? Some 1503 before" or "ends after" a grace period? Some aspects of the meaning
1587 are pretty obvious, as in the example above, 1504 are pretty obvious, as in the example above, but the details aren't
1588 entirely clear. The LKMM formalizes this not 1505 entirely clear. The LKMM formalizes this notion by means of the
1589 rcu-link relation. rcu-link encompasses a ve 1506 rcu-link relation. rcu-link encompasses a very general notion of
1590 "before": If E and F are RCU fence events (i. !! 1507 "before": Among other things, X ->rcu-link Z includes cases where X
1591 rcu_read_unlock(), or synchronize_rcu()) then !! 1508 happens-before or is equal to some event Y which is equal to or comes
1592 E ->rcu-link F includes cases where E is po-b !! 1509 before Z in the coherence order. When Y = Z this says that X ->rfe Z
1593 event X, F is po-after some memory-access eve !! 1510 implies X ->rcu-link Z. In addition, when Y = X it says that X ->fr Z
1594 X ->rfe Y, X ->co Y, or X ->fr Y. !! 1511 and X ->co Z each imply X ->rcu-link Z.
1595 1512
1596 The formal definition of the rcu-link relatio 1513 The formal definition of the rcu-link relation is more than a little
1597 obscure, and we won't give it here. It is cl 1514 obscure, and we won't give it here. It is closely related to the pb
1598 relation, and the details don't matter unless 1515 relation, and the details don't matter unless you want to comb through
1599 a somewhat lengthy formal proof. Pretty much 1516 a somewhat lengthy formal proof. Pretty much all you need to know
1600 about rcu-link is the information in the prec 1517 about rcu-link is the information in the preceding paragraph.
1601 1518
1602 The LKMM also defines the rcu-gp and rcu-rscs !! 1519 The LKMM also defines the gp and rscs relations. They bring grace
1603 grace periods and read-side critical sections !! 1520 periods and read-side critical sections into the picture, in the
1604 following way: 1521 following way:
1605 1522
1606 E ->rcu-gp F means that E and F are i !! 1523 E ->gp F means there is a synchronize_rcu() fence event S such
1607 and that event is a synchronize_rcu() !! 1524 that E ->po S and either S ->po F or S = F. In simple terms,
1608 period). !! 1525 there is a grace period po-between E and F.
1609 !! 1526
1610 E ->rcu-rscsi F means that E and F ar !! 1527 E ->rscs F means there is a critical section delimited by an
1611 and rcu_read_lock() fence events deli !! 1528 rcu_read_lock() fence L and an rcu_read_unlock() fence U, such
1612 critical section. (The 'i' at the en !! 1529 that E ->po U and either L ->po F or L = F. You can think of
1613 that this relation is "inverted": It !! 1530 this as saying that E and F are in the same critical section
1614 critical section to the start.) !! 1531 (in fact, it also allows E to be po-before the start of the
>> 1532 critical section and F to be po-after the end).
1615 1533
1616 If we think of the rcu-link relation as stand 1534 If we think of the rcu-link relation as standing for an extended
1617 "before", then X ->rcu-gp Y ->rcu-link Z roug !! 1535 "before", then X ->gp Y ->rcu-link Z says that X executes before a
1618 grace period which ends before Z begins. (In !! 1536 grace period which ends before Z executes. (In fact it covers more
1619 this, because it also includes cases where so !! 1537 than this, because it also includes cases where X executes before a
1620 Z's CPU before Z begins but doesn't propagate !! 1538 grace period and some store propagates to Z's CPU before Z executes
1621 after X ends.) Similarly, X ->rcu-rscsi Y -> !! 1539 but doesn't propagate to some other CPU until after the grace period
1622 the end of a critical section which starts be !! 1540 ends.) Similarly, X ->rscs Y ->rcu-link Z says that X is part of (or
1623 !! 1541 before the start of) a critical section which starts before Z
1624 The LKMM goes on to define the rcu-order rela !! 1542 executes.
1625 rcu-gp and rcu-rscsi links separated by rcu-l !! 1543
1626 number of rcu-gp links is >= the number of rc !! 1544 The LKMM goes on to define the rcu-fence relation as a sequence of gp
1627 example: !! 1545 and rscs links separated by rcu-link links, in which the number of gp
>> 1546 links is >= the number of rscs links. For example:
>> 1547
>> 1548 X ->gp Y ->rcu-link Z ->rscs T ->rcu-link U ->gp V
1628 1549
1629 X ->rcu-gp Y ->rcu-link Z ->rcu-rscsi !! 1550 would imply that X ->rcu-fence V, because this sequence contains two
>> 1551 gp links and only one rscs link. (It also implies that X ->rcu-fence T
>> 1552 and Z ->rcu-fence V.) On the other hand:
1630 1553
1631 would imply that X ->rcu-order V, because thi !! 1554 X ->rscs Y ->rcu-link Z ->rscs T ->rcu-link U ->gp V
1632 rcu-gp links and one rcu-rscsi link. (It als !! 1555
1633 X ->rcu-order T and Z ->rcu-order V.) On the !! 1556 does not imply X ->rcu-fence V, because the sequence contains only
1634 !! 1557 one gp link but two rscs links.
1635 X ->rcu-rscsi Y ->rcu-link Z ->rcu-rs !! 1558
1636 !! 1559 The rcu-fence relation is important because the Grace Period Guarantee
1637 does not imply X ->rcu-order V, because the s !! 1560 means that rcu-fence acts kind of like a strong fence. In particular,
1638 one rcu-gp link but two rcu-rscsi links. !! 1561 if W is a write and we have W ->rcu-fence Z, the Guarantee says that W
1639 !! 1562 will propagate to every CPU before Z executes.
1640 The rcu-order relation is important because t <<
1641 means that rcu-order links act kind of like s <<
1642 particular, E ->rcu-order F implies not only <<
1643 ends, but also that any write po-before E wil <<
1644 before any instruction po-after F can execute <<
1645 imply that E must execute before F; in fact, <<
1646 fence event is linked to itself by rcu-order <<
1647 1563
1648 To prove this in full generality requires som 1564 To prove this in full generality requires some intellectual effort.
1649 We'll consider just a very simple case: 1565 We'll consider just a very simple case:
1650 1566
1651 G ->rcu-gp W ->rcu-link Z ->rcu-rscsi !! 1567 W ->gp X ->rcu-link Y ->rscs Z.
>> 1568
>> 1569 This formula means that there is a grace period G and a critical
>> 1570 section C such that:
>> 1571
>> 1572 1. W is po-before G;
>> 1573
>> 1574 2. X is equal to or po-after G;
1652 1575
1653 This formula means that G and W are the same !! 1576 3. X comes "before" Y in some sense;
1654 and there are events X, Y and a read-side cri <<
1655 1577
1656 1. G = W is po-before or equal to X; !! 1578 4. Y is po-before the end of C;
1657 1579
1658 2. X comes "before" Y in some sense ( !! 1580 5. Z is equal to or po-after the start of C.
1659 1581
1660 3. Y is po-before Z; !! 1582 From 2 - 4 we deduce that the grace period G ends before the critical
1661 !! 1583 section C. Then the second part of the Grace Period Guarantee says
1662 4. Z is the rcu_read_unlock() event m !! 1584 not only that G starts before C does, but also that W (which executes
1663 !! 1585 on G's CPU before G starts) must propagate to every CPU before C
1664 5. F is the rcu_read_lock() event mar !! 1586 starts. In particular, W propagates to every CPU before Z executes
1665 !! 1587 (or finishes executing, in the case where Z is equal to the
1666 From 1 - 4 we deduce that the grace period G !! 1588 rcu_read_lock() fence event which starts C.) This sort of reasoning
1667 section C. Then part (2) of the Grace Period !! 1589 can be expanded to handle all the situations covered by rcu-fence.
1668 that G starts before C does, but also that an <<
1669 G's CPU before G starts must propagate to eve <<
1670 In particular, the write propagates to every <<
1671 executing and hence before any instruction po <<
1672 This sort of reasoning can be extended to han <<
1673 covered by rcu-order. <<
1674 <<
1675 The rcu-fence relation is a simple extension <<
1676 rcu-order only links certain fence events (ca <<
1677 rcu_read_lock(), or rcu_read_unlock()), rcu-f <<
1678 that are separated by an rcu-order link. Thi <<
1679 the strong-fence relation links events that a <<
1680 smp_mb() fence event (as mentioned above, rcu <<
1681 like strong fences). Written symbolically, X <<
1682 there are fence events E and F such that: <<
1683 <<
1684 X ->po E ->rcu-order F ->po Y. <<
1685 <<
1686 From the discussion above, we see this implie <<
1687 executes before Y, but also (if X is a store) <<
1688 every CPU before Y executes. Thus rcu-fence <<
1689 "super-strong" fence: Unlike the original str <<
1690 synchronize_rcu()), rcu-fence is able to link <<
1691 CPUs. (Perhaps this fact should lead us to s <<
1692 really a fence at all!) <<
1693 1590
1694 Finally, the LKMM defines the RCU-before (rb) 1591 Finally, the LKMM defines the RCU-before (rb) relation in terms of
1695 rcu-fence. This is done in essentially the s 1592 rcu-fence. This is done in essentially the same way as the pb
1696 relation was defined in terms of strong-fence 1593 relation was defined in terms of strong-fence. We will omit the
1697 details; the end result is that E ->rb F impl !! 1594 details; the end result is that E ->rb F implies E must execute before
1698 before F, just as E ->pb F does (and for much !! 1595 F, just as E ->pb F does (and for much the same reasons).
1699 1596
1700 Putting this all together, the LKMM expresses 1597 Putting this all together, the LKMM expresses the Grace Period
1701 Guarantee by requiring that the rb relation d 1598 Guarantee by requiring that the rb relation does not contain a cycle.
1702 Equivalently, this "rcu" axiom requires that !! 1599 Equivalently, this "rcu" axiom requires that there are no events E and
1703 and F with E ->rcu-link F ->rcu-order E. Or !! 1600 F with E ->rcu-link F ->rcu-fence E. Or to put it a third way, the
1704 the axiom requires that there are no cycles c !! 1601 axiom requires that there are no cycles consisting of gp and rscs
1705 rcu-rscsi alternating with rcu-link, where th !! 1602 alternating with rcu-link, where the number of gp links is >= the
1706 is >= the number of rcu-rscsi links. !! 1603 number of rscs links.
1707 1604
1708 Justifying the axiom isn't easy, but it is in 1605 Justifying the axiom isn't easy, but it is in fact a valid
1709 formalization of the Grace Period Guarantee. 1606 formalization of the Grace Period Guarantee. We won't attempt to go
1710 through the detailed argument, but the follow 1607 through the detailed argument, but the following analysis gives a
1711 taste of what is involved. Suppose both part !! 1608 taste of what is involved. Suppose we have a violation of the first
1712 violated: A critical section starts before a !! 1609 part of the Guarantee: A critical section starts before a grace
1713 store propagates to the critical section's CP !! 1610 period, and some store propagates to the critical section's CPU before
1714 critical section but doesn't propagate to som !! 1611 the end of the critical section but doesn't propagate to some other
1715 the end of the grace period. !! 1612 CPU until after the end of the grace period.
1716 1613
1717 Putting symbols to these ideas, let L and U b 1614 Putting symbols to these ideas, let L and U be the rcu_read_lock() and
1718 rcu_read_unlock() fence events delimiting the 1615 rcu_read_unlock() fence events delimiting the critical section in
1719 question, and let S be the synchronize_rcu() 1616 question, and let S be the synchronize_rcu() fence event for the grace
1720 period. Saying that the critical section sta 1617 period. Saying that the critical section starts before S means there
1721 are events Q and R where Q is po-after L (whi !! 1618 are events E and F where E is po-after L (which marks the start of the
1722 critical section), Q is "before" R in the sen !! 1619 critical section), E is "before" F in the sense of the rcu-link
1723 relation, and R is po-before the grace period !! 1620 relation, and F is po-before the grace period S:
1724 1621
1725 L ->rcu-link S. !! 1622 L ->po E ->rcu-link F ->po S.
1726 1623
1727 Let W be the store mentioned above, let Y com !! 1624 Let W be the store mentioned above, let Z come before the end of the
1728 critical section and witness that W propagate 1625 critical section and witness that W propagates to the critical
1729 section's CPU by reading from W, and let Z on !! 1626 section's CPU by reading from W, and let Y on some arbitrary CPU be a
1730 witness that W has not propagated to that CPU !! 1627 witness that W has not propagated to that CPU, where Y happens after
1731 some event X which is po-after S. Symbolical 1628 some event X which is po-after S. Symbolically, this amounts to:
1732 1629
1733 S ->po X ->hb* Z ->fr W ->rf Y ->po U !! 1630 S ->po X ->hb* Y ->fr W ->rf Z ->po U.
1734 1631
1735 The fr link from Z to W indicates that W has !! 1632 The fr link from Y to W indicates that W has not propagated to Y's CPU
1736 at the time that Z executes. From this, it c !! 1633 at the time that Y executes. From this, it can be shown (see the
1737 discussion of the rcu-link relation earlier) !! 1634 discussion of the rcu-link relation earlier) that X and Z are related
1738 by rcu-link: !! 1635 by rcu-link, yielding:
1739 1636
1740 S ->rcu-link U. !! 1637 S ->po X ->rcu-link Z ->po U.
1741 1638
1742 Since S is a grace period we have S ->rcu-gp !! 1639 The formulas say that S is po-between F and X, hence F ->gp X. They
1743 the start and end of the critical section C w !! 1640 also say that Z comes before the end of the critical section and E
1744 From this we obtain: !! 1641 comes after its start, hence Z ->rscs E. From all this we obtain:
1745 1642
1746 S ->rcu-gp S ->rcu-link U ->rcu-rscsi !! 1643 F ->gp X ->rcu-link Z ->rscs E ->rcu-link F,
1747 1644
1748 a forbidden cycle. Thus the "rcu" axiom rule 1645 a forbidden cycle. Thus the "rcu" axiom rules out this violation of
1749 the Grace Period Guarantee. 1646 the Grace Period Guarantee.
1750 1647
1751 For something a little more down-to-earth, le 1648 For something a little more down-to-earth, let's see how the axiom
1752 works out in practice. Consider the RCU code 1649 works out in practice. Consider the RCU code example from above, this
1753 time with statement labels added: !! 1650 time with statement labels added to the memory access instructions:
1754 1651
1755 int x, y; 1652 int x, y;
1756 1653
1757 P0() 1654 P0()
1758 { 1655 {
1759 L: rcu_read_lock(); !! 1656 rcu_read_lock();
1760 X: WRITE_ONCE(x, 1); !! 1657 W: WRITE_ONCE(x, 1);
1761 Y: WRITE_ONCE(y, 1); !! 1658 X: WRITE_ONCE(y, 1);
1762 U: rcu_read_unlock(); !! 1659 rcu_read_unlock();
1763 } 1660 }
1764 1661
1765 P1() 1662 P1()
1766 { 1663 {
1767 int r1, r2; 1664 int r1, r2;
1768 1665
1769 Z: r1 = READ_ONCE(x); !! 1666 Y: r1 = READ_ONCE(x);
1770 S: synchronize_rcu(); !! 1667 synchronize_rcu();
1771 W: r2 = READ_ONCE(y); !! 1668 Z: r2 = READ_ONCE(y);
1772 } 1669 }
1773 1670
1774 1671
1775 If r2 = 0 at the end then P0's store at Y ove !! 1672 If r2 = 0 at the end then P0's store at X overwrites the value that
1776 P1's load at W reads from, so we have W ->fre !! 1673 P1's load at Z reads from, so we have Z ->fre X and thus Z ->rcu-link X.
1777 also Y ->po U, we get S ->rcu-link U. In add !! 1674 In addition, there is a synchronize_rcu() between Y and Z, so therefore
1778 because S is a grace period. !! 1675 we have Y ->gp Z.
1779 1676
1780 If r1 = 1 at the end then P1's load at Z read !! 1677 If r1 = 1 at the end then P1's load at Y reads from P0's store at W,
1781 so we have X ->rfe Z. Together with L ->po X !! 1678 so we have W ->rcu-link Y. In addition, W and X are in the same critical
1782 yields L ->rcu-link S. And since L and U are !! 1679 section, so therefore we have X ->rscs W.
1783 critical section, we have U ->rcu-rscsi L. <<
1784 1680
1785 Then U ->rcu-rscsi L ->rcu-link S ->rcu-gp S !! 1681 Then X ->rscs W ->rcu-link Y ->gp Z ->rcu-link X is a forbidden cycle,
1786 forbidden cycle, violating the "rcu" axiom. !! 1682 violating the "rcu" axiom. Hence the outcome is not allowed by the
1787 allowed by the LKMM, as we would expect. !! 1683 LKMM, as we would expect.
1788 1684
1789 For contrast, let's see what can happen in a 1685 For contrast, let's see what can happen in a more complicated example:
1790 1686
1791 int x, y, z; 1687 int x, y, z;
1792 1688
1793 P0() 1689 P0()
1794 { 1690 {
1795 int r0; 1691 int r0;
1796 1692
1797 L0: rcu_read_lock(); !! 1693 rcu_read_lock();
1798 r0 = READ_ONCE(x); !! 1694 W: r0 = READ_ONCE(x);
1799 WRITE_ONCE(y, 1); !! 1695 X: WRITE_ONCE(y, 1);
1800 U0: rcu_read_unlock(); !! 1696 rcu_read_unlock();
1801 } 1697 }
1802 1698
1803 P1() 1699 P1()
1804 { 1700 {
1805 int r1; 1701 int r1;
1806 1702
1807 r1 = READ_ONCE(y); !! 1703 Y: r1 = READ_ONCE(y);
1808 S1: synchronize_rcu(); !! 1704 synchronize_rcu();
1809 WRITE_ONCE(z, 1); !! 1705 Z: WRITE_ONCE(z, 1);
1810 } 1706 }
1811 1707
1812 P2() 1708 P2()
1813 { 1709 {
1814 int r2; 1710 int r2;
1815 1711
1816 L2: rcu_read_lock(); !! 1712 rcu_read_lock();
1817 r2 = READ_ONCE(z); !! 1713 U: r2 = READ_ONCE(z);
1818 WRITE_ONCE(x, 1); !! 1714 V: WRITE_ONCE(x, 1);
1819 U2: rcu_read_unlock(); !! 1715 rcu_read_unlock();
1820 } 1716 }
1821 1717
1822 If r0 = r1 = r2 = 1 at the end, then similar 1718 If r0 = r1 = r2 = 1 at the end, then similar reasoning to before shows
1823 that U0 ->rcu-rscsi L0 ->rcu-link S1 ->rcu-gp !! 1719 that W ->rscs X ->rcu-link Y ->gp Z ->rcu-link U ->rscs V ->rcu-link W.
1824 L2 ->rcu-link U0. However this cycle is not !! 1720 However this cycle is not forbidden, because the sequence of relations
1825 sequence of relations contains fewer instance !! 1721 contains fewer instances of gp (one) than of rscs (two). Consequently
1826 rcu-rscsi (two). Consequently the outcome is !! 1722 the outcome is allowed by the LKMM. The following instruction timing
1827 The following instruction timing diagram show !! 1723 diagram shows how it might actually occur:
1828 occur: <<
1829 1724
1830 P0 P1 1725 P0 P1 P2
1831 -------------------- -------------------- 1726 -------------------- -------------------- --------------------
1832 rcu_read_lock() 1727 rcu_read_lock()
1833 WRITE_ONCE(y, 1) !! 1728 X: WRITE_ONCE(y, 1)
1834 r1 = READ_ONCE(y) !! 1729 Y: r1 = READ_ONCE(y)
1835 synchronize_rcu() sta 1730 synchronize_rcu() starts
1836 . 1731 . rcu_read_lock()
1837 . !! 1732 . V: WRITE_ONCE(x, 1)
1838 r0 = READ_ONCE(x) . !! 1733 W: r0 = READ_ONCE(x) .
1839 rcu_read_unlock() . 1734 rcu_read_unlock() .
1840 synchronize_rcu() end 1735 synchronize_rcu() ends
1841 WRITE_ONCE(z, 1) !! 1736 Z: WRITE_ONCE(z, 1)
1842 !! 1737 U: r2 = READ_ONCE(z)
1843 1738 rcu_read_unlock()
1844 1739
1845 This requires P0 and P2 to execute their load 1740 This requires P0 and P2 to execute their loads and stores out of
1846 program order, but of course they are allowed 1741 program order, but of course they are allowed to do so. And as you
1847 can see, the Grace Period Guarantee is not vi 1742 can see, the Grace Period Guarantee is not violated: The critical
1848 section in P0 both starts before P1's grace p 1743 section in P0 both starts before P1's grace period does and ends
1849 before it does, and the critical section in P 1744 before it does, and the critical section in P2 both starts after P1's
1850 grace period does and ends after it does. 1745 grace period does and ends after it does.
1851 1746
1852 The LKMM supports SRCU (Sleepable Read-Copy-U <<
1853 normal RCU. The ideas involved are much the <<
1854 relations srcu-gp and srcu-rscsi added to rep <<
1855 and read-side critical sections. However, th <<
1856 differences between RCU read-side critical se <<
1857 counterparts, as described in the next sectio <<
1858 <<
1859 <<
1860 SRCU READ-SIDE CRITICAL SECTIONS <<
1861 -------------------------------- <<
1862 <<
1863 The LKMM uses the srcu-rscsi relation to mode <<
1864 sections. They differ from RCU read-side cri <<
1865 following respects: <<
1866 <<
1867 1. Unlike the analogous RCU primitives, <<
1868 srcu_read_lock(), and srcu_read_unloc <<
1869 struct srcu_struct as an argument. T <<
1870 an SRCU domain, and calls linked by s <<
1871 same domain. Read-side critical sect <<
1872 associated with different domains are <<
1873 another; the SRCU version of the RCU <<
1874 to pairs of critical sections and gra <<
1875 same domain. <<
1876 <<
1877 2. srcu_read_lock() returns a value, cal <<
1878 be passed to the matching srcu_read_u <<
1879 rcu_read_lock() and rcu_read_unlock() <<
1880 call does not always have to match th <<
1881 srcu_read_unlock(). In fact, it is p <<
1882 read-side critical sections to overla <<
1883 following example (where s is an srcu <<
1884 are integer variables): <<
1885 <<
1886 idx1 = srcu_read_lock(&s); <<
1887 idx2 = srcu_read_lock(&s); <<
1888 srcu_read_unlock(&s, idx1); <<
1889 srcu_read_unlock(&s, idx2); <<
1890 <<
1891 The matching is determined entirely b <<
1892 index value. By contrast, if the cal <<
1893 rcu_read_lock() and rcu_read_unlock() <<
1894 created two nested (fully overlapping <<
1895 sections: an inner one and an outer o <<
1896 <<
1897 3. The srcu_down_read() and srcu_up_read <<
1898 exactly like srcu_read_lock() and src <<
1899 that matching calls don't have to exe <<
1900 (The names are meant to be suggestive <<
1901 semaphores.) Since the matching is d <<
1902 pointer and index value, these primit <<
1903 an SRCU read-side critical section to <<
1904 on another, so to speak. <<
1905 <<
1906 In order to account for these properties of S <<
1907 srcu_read_lock() as a special type of load ev <<
1908 appropriate, since it takes a memory location <<
1909 a value, just as a load does) and srcu_read_u <<
1910 of store event (again appropriate, since it t <<
1911 memory location and a value). These loads an <<
1912 belonging to the "srcu-lock" and "srcu-unlock <<
1913 respectively. <<
1914 <<
1915 This approach allows the LKMM to tell whether <<
1916 associated with the same SRCU domain, simply <<
1917 access the same memory location (i.e., they a <<
1918 relation). It also gives a way to tell which <<
1919 particular lock, by checking for the presence <<
1920 from the load (srcu-lock) to the store (srcu- <<
1921 given the situation outlined earlier (with st <<
1922 <<
1923 A: idx1 = srcu_read_lock(&s); <<
1924 B: idx2 = srcu_read_lock(&s); <<
1925 C: srcu_read_unlock(&s, idx1); <<
1926 D: srcu_read_unlock(&s, idx2); <<
1927 <<
1928 the LKMM will treat A and B as loads from s y <<
1929 idx1 and idx2 respectively. Similarly, it wi <<
1930 though they stored the values from idx1 and i <<
1931 is much as if we had written: <<
1932 <<
1933 A: idx1 = READ_ONCE(s); <<
1934 B: idx2 = READ_ONCE(s); <<
1935 C: WRITE_ONCE(s, idx1); <<
1936 D: WRITE_ONCE(s, idx2); <<
1937 <<
1938 except for the presence of the special srcu-l <<
1939 annotations. You can see at once that we hav <<
1940 B ->data D. These dependencies tell the LKMM <<
1941 srcu-unlock event matching srcu-lock event A, <<
1942 srcu-unlock event matching srcu-lock event B. <<
1943 <<
1944 This approach is admittedly a hack, and it ha <<
1945 to problems. For example, in: <<
1946 <<
1947 idx1 = srcu_read_lock(&s); <<
1948 srcu_read_unlock(&s, idx1); <<
1949 idx2 = srcu_read_lock(&s); <<
1950 srcu_read_unlock(&s, idx2); <<
1951 <<
1952 the LKMM will believe that idx2 must have the <<
1953 since it reads from the immediately preceding <<
1954 Fortunately this won't matter, assuming that <<
1955 anything with SRCU index values other than pa <<
1956 srcu_read_unlock() or srcu_up_read() calls. <<
1957 <<
1958 However, sometimes it is necessary to store a <<
1959 shared variable temporarily. In fact, this i <<
1960 srcu_down_read() to pass the index it gets to <<
1961 on a different CPU. In more detail, we might <<
1962 <<
1963 struct srcu_struct s; <<
1964 int x; <<
1965 <<
1966 P0() <<
1967 { <<
1968 int r0; <<
1969 <<
1970 A: r0 = srcu_down_read(&s); <<
1971 B: WRITE_ONCE(x, r0); <<
1972 } <<
1973 <<
1974 P1() <<
1975 { <<
1976 int r1; <<
1977 <<
1978 C: r1 = READ_ONCE(x); <<
1979 D: srcu_up_read(&s, r1); <<
1980 } <<
1981 <<
1982 Assuming that P1 executes after P0 and does r <<
1983 stored in x, we can write this (using bracket <<
1984 annotations) as: <<
1985 <<
1986 A[srcu-lock] ->data B[once] ->rf C[on <<
1987 <<
1988 The LKMM defines a carry-srcu-data relation t <<
1989 it permits an arbitrarily long sequence of <<
1990 <<
1991 data ; rf <<
1992 <<
1993 pairs (that is, a data link followed by an rf <<
1994 an srcu-lock event and the final data depende <<
1995 matching srcu-unlock event. carry-srcu-data <<
1996 need to ensure that none of the intermediate <<
1997 sequence are instances of srcu-unlock. This <<
1998 pattern like the one above: <<
1999 <<
2000 A: idx1 = srcu_read_lock(&s); <<
2001 B: srcu_read_unlock(&s, idx1); <<
2002 C: idx2 = srcu_read_lock(&s); <<
2003 D: srcu_read_unlock(&s, idx2); <<
2004 <<
2005 the LKMM treats B as a store to the variable <<
2006 that variable, creating an undesirable rf lin <<
2007 <<
2008 A ->data B ->rf C ->data D. <<
2009 <<
2010 This would cause carry-srcu-data to mistakenl <<
2011 dependency from A to D, giving the impression <<
2012 srcu-unlock event matching A's srcu-lock. To <<
2013 carry-srcu-data does not accept sequences in <<
2014 the intermediate ->data links (B above) is an <<
2015 <<
2016 1747
2017 LOCKING 1748 LOCKING
2018 ------- 1749 -------
2019 1750
2020 The LKMM includes locking. In fact, there is 1751 The LKMM includes locking. In fact, there is special code for locking
2021 in the formal model, added in order to make t 1752 in the formal model, added in order to make tools run faster.
2022 However, this special code is intended to be 1753 However, this special code is intended to be more or less equivalent
2023 to concepts we have already covered. A spinl 1754 to concepts we have already covered. A spinlock_t variable is treated
2024 the same as an int, and spin_lock(&s) is trea 1755 the same as an int, and spin_lock(&s) is treated almost the same as:
2025 1756
2026 while (cmpxchg_acquire(&s, 0, 1) != 0 1757 while (cmpxchg_acquire(&s, 0, 1) != 0)
2027 cpu_relax(); 1758 cpu_relax();
2028 1759
2029 This waits until s is equal to 0 and then ato 1760 This waits until s is equal to 0 and then atomically sets it to 1,
2030 and the read part of the cmpxchg operation ac 1761 and the read part of the cmpxchg operation acts as an acquire fence.
2031 An alternate way to express the same thing wo 1762 An alternate way to express the same thing would be:
2032 1763
2033 r = xchg_acquire(&s, 1); 1764 r = xchg_acquire(&s, 1);
2034 1765
2035 along with a requirement that at the end, r = 1766 along with a requirement that at the end, r = 0. Similarly,
2036 spin_trylock(&s) is treated almost the same a 1767 spin_trylock(&s) is treated almost the same as:
2037 1768
2038 return !cmpxchg_acquire(&s, 0, 1); 1769 return !cmpxchg_acquire(&s, 0, 1);
2039 1770
2040 which atomically sets s to 1 if it is current 1771 which atomically sets s to 1 if it is currently equal to 0 and returns
2041 true if it succeeds (the read part of the cmp 1772 true if it succeeds (the read part of the cmpxchg operation acts as an
2042 acquire fence only if the operation is succes 1773 acquire fence only if the operation is successful). spin_unlock(&s)
2043 is treated almost the same as: 1774 is treated almost the same as:
2044 1775
2045 smp_store_release(&s, 0); 1776 smp_store_release(&s, 0);
2046 1777
2047 The "almost" qualifiers above need some expla 1778 The "almost" qualifiers above need some explanation. In the LKMM, the
2048 store-release in a spin_unlock() and the load 1779 store-release in a spin_unlock() and the load-acquire which forms the
2049 first half of the atomic rmw update in a spin 1780 first half of the atomic rmw update in a spin_lock() or a successful
2050 spin_trylock() -- we can call these things lo 1781 spin_trylock() -- we can call these things lock-releases and
2051 lock-acquires -- have two properties beyond t 1782 lock-acquires -- have two properties beyond those of ordinary releases
2052 and acquires. 1783 and acquires.
2053 1784
2054 First, when a lock-acquire reads from or is p !! 1785 First, when a lock-acquire reads from a lock-release, the LKMM
2055 the LKMM requires that every instruction po-b !! 1786 requires that every instruction po-before the lock-release must
2056 must execute before any instruction po-after !! 1787 execute before any instruction po-after the lock-acquire. This would
2057 would naturally hold if the release and acqui !! 1788 naturally hold if the release and acquire operations were on different
2058 different CPUs and accessed the same lock var !! 1789 CPUs, but the LKMM says it holds even when they are on the same CPU.
2059 it also holds when they are on the same CPU, !! 1790 For example:
2060 different lock variables. For example: <<
2061 1791
2062 int x, y; 1792 int x, y;
2063 spinlock_t s, t; !! 1793 spinlock_t s;
2064 1794
2065 P0() 1795 P0()
2066 { 1796 {
2067 int r1, r2; 1797 int r1, r2;
2068 1798
2069 spin_lock(&s); 1799 spin_lock(&s);
2070 r1 = READ_ONCE(x); 1800 r1 = READ_ONCE(x);
2071 spin_unlock(&s); 1801 spin_unlock(&s);
2072 spin_lock(&t); !! 1802 spin_lock(&s);
2073 r2 = READ_ONCE(y); 1803 r2 = READ_ONCE(y);
2074 spin_unlock(&t); !! 1804 spin_unlock(&s);
2075 } 1805 }
2076 1806
2077 P1() 1807 P1()
2078 { 1808 {
2079 WRITE_ONCE(y, 1); 1809 WRITE_ONCE(y, 1);
2080 smp_wmb(); 1810 smp_wmb();
2081 WRITE_ONCE(x, 1); 1811 WRITE_ONCE(x, 1);
2082 } 1812 }
2083 1813
2084 Here the second spin_lock() is po-after the f !! 1814 Here the second spin_lock() reads from the first spin_unlock(), and
2085 therefore the load of x must execute before t !! 1815 therefore the load of x must execute before the load of y. Thus we
2086 the two locking operations use different lock !! 1816 cannot have r1 = 1 and r2 = 0 at the end (this is an instance of the
2087 r1 = 1 and r2 = 0 at the end (this is an inst !! 1817 MP pattern).
2088 1818
2089 This requirement does not apply to ordinary r 1819 This requirement does not apply to ordinary release and acquire
2090 fences, only to lock-related operations. For 1820 fences, only to lock-related operations. For instance, suppose P0()
2091 in the example had been written as: 1821 in the example had been written as:
2092 1822
2093 P0() 1823 P0()
2094 { 1824 {
2095 int r1, r2, r3; 1825 int r1, r2, r3;
2096 1826
2097 r1 = READ_ONCE(x); 1827 r1 = READ_ONCE(x);
2098 smp_store_release(&s, 1); 1828 smp_store_release(&s, 1);
2099 r3 = smp_load_acquire(&s); 1829 r3 = smp_load_acquire(&s);
2100 r2 = READ_ONCE(y); 1830 r2 = READ_ONCE(y);
2101 } 1831 }
2102 1832
2103 Then the CPU would be allowed to forward the 1833 Then the CPU would be allowed to forward the s = 1 value from the
2104 smp_store_release() to the smp_load_acquire() 1834 smp_store_release() to the smp_load_acquire(), executing the
2105 instructions in the following order: 1835 instructions in the following order:
2106 1836
2107 r3 = smp_load_acquire(&s); 1837 r3 = smp_load_acquire(&s); // Obtains r3 = 1
2108 r2 = READ_ONCE(y); 1838 r2 = READ_ONCE(y);
2109 r1 = READ_ONCE(x); 1839 r1 = READ_ONCE(x);
2110 smp_store_release(&s, 1); 1840 smp_store_release(&s, 1); // Value is forwarded
2111 1841
2112 and thus it could load y before x, obtaining 1842 and thus it could load y before x, obtaining r2 = 0 and r1 = 1.
2113 1843
2114 Second, when a lock-acquire reads from or is !! 1844 Second, when a lock-acquire reads from a lock-release, and some other
2115 and some other stores W and W' occur po-befor !! 1845 stores W and W' occur po-before the lock-release and po-after the
2116 po-after the lock-acquire respectively, the L !! 1846 lock-acquire respectively, the LKMM requires that W must propagate to
2117 propagate to each CPU before W' does. For ex !! 1847 each CPU before W' does. For example, consider:
2118 1848
2119 int x, y; 1849 int x, y;
2120 spinlock_t s; !! 1850 spinlock_t x;
2121 1851
2122 P0() 1852 P0()
2123 { 1853 {
2124 spin_lock(&s); 1854 spin_lock(&s);
2125 WRITE_ONCE(x, 1); 1855 WRITE_ONCE(x, 1);
2126 spin_unlock(&s); 1856 spin_unlock(&s);
2127 } 1857 }
2128 1858
2129 P1() 1859 P1()
2130 { 1860 {
2131 int r1; 1861 int r1;
2132 1862
2133 spin_lock(&s); 1863 spin_lock(&s);
2134 r1 = READ_ONCE(x); 1864 r1 = READ_ONCE(x);
2135 WRITE_ONCE(y, 1); 1865 WRITE_ONCE(y, 1);
2136 spin_unlock(&s); 1866 spin_unlock(&s);
2137 } 1867 }
2138 1868
2139 P2() 1869 P2()
2140 { 1870 {
2141 int r2, r3; 1871 int r2, r3;
2142 1872
2143 r2 = READ_ONCE(y); 1873 r2 = READ_ONCE(y);
2144 smp_rmb(); 1874 smp_rmb();
2145 r3 = READ_ONCE(x); 1875 r3 = READ_ONCE(x);
2146 } 1876 }
2147 1877
2148 If r1 = 1 at the end then the spin_lock() in 1878 If r1 = 1 at the end then the spin_lock() in P1 must have read from
2149 the spin_unlock() in P0. Hence the store to 1879 the spin_unlock() in P0. Hence the store to x must propagate to P2
2150 before the store to y does, so we cannot have !! 1880 before the store to y does, so we cannot have r2 = 1 and r3 = 0.
2151 if P1 had used a lock variable different from <<
2152 propagated in either order. (On the other ha <<
2153 P1 had all executed on a single CPU, as in th <<
2154 one, then the writes would have propagated in <<
2155 critical sections used different lock variabl <<
2156 1881
2157 These two special requirements for lock-relea 1882 These two special requirements for lock-release and lock-acquire do
2158 not arise from the operational model. Nevert 1883 not arise from the operational model. Nevertheless, kernel developers
2159 have come to expect and rely on them because 1884 have come to expect and rely on them because they do hold on all
2160 architectures supported by the Linux kernel, 1885 architectures supported by the Linux kernel, albeit for various
2161 differing reasons. 1886 differing reasons.
2162 1887
2163 1888
2164 PLAIN ACCESSES AND DATA RACES <<
2165 ----------------------------- <<
2166 <<
2167 In the LKMM, memory accesses such as READ_ONC <<
2168 smp_load_acquire(&z), and so on are collectiv <<
2169 "marked" accesses, because they are all annot <<
2170 operations of one kind or another. Ordinary <<
2171 accesses such as x or y = 0 are simply called <<
2172 <<
2173 Early versions of the LKMM had nothing to say <<
2174 The C standard allows compilers to assume tha <<
2175 by plain accesses are not concurrently read o <<
2176 threads or CPUs. This leaves compilers free <<
2177 of transformations or optimizations of code c <<
2178 making such code very difficult for a memory <<
2179 <<
2180 Here is just one example of a possible pitfal <<
2181 <<
2182 int a = 6; <<
2183 int *x = &a; <<
2184 <<
2185 P0() <<
2186 { <<
2187 int *r1; <<
2188 int r2 = 0; <<
2189 <<
2190 r1 = x; <<
2191 if (r1 != NULL) <<
2192 r2 = READ_ONCE(*r1); <<
2193 } <<
2194 <<
2195 P1() <<
2196 { <<
2197 WRITE_ONCE(x, NULL); <<
2198 } <<
2199 <<
2200 On the face of it, one would expect that when <<
2201 possible final values for r2 are 6 and 0, dep <<
2202 P1's store to x propagates to P0 before P0's <<
2203 But since P0's load from x is a plain access, <<
2204 to carry out the load twice (for the comparis <<
2205 for the READ_ONCE()) and eliminate the tempor <<
2206 object code generated for P0 could therefore <<
2207 like this: <<
2208 <<
2209 P0() <<
2210 { <<
2211 int r2 = 0; <<
2212 <<
2213 if (x != NULL) <<
2214 r2 = READ_ONCE(*x); <<
2215 } <<
2216 <<
2217 And now it is obvious that this code runs the <<
2218 NULL pointer, because P1's store to x might p <<
2219 test against NULL has been made but before th <<
2220 If the original code had said "r1 = READ_ONCE <<
2221 the compiler would not have performed this op <<
2222 would be no possibility of a NULL-pointer der <<
2223 <<
2224 Given the possibility of transformations like <<
2225 doesn't try to predict all possible outcomes <<
2226 accesses. It is instead content to determine <<
2227 violates the compiler's assumptions, which wo <<
2228 outcome undefined. <<
2229 <<
2230 In technical terms, the compiler is allowed t <<
2231 program executes, there will not be any data <<
2232 occurs when there are two memory accesses suc <<
2233 <<
2234 1. they access the same location, <<
2235 <<
2236 2. at least one of them is a store, <<
2237 <<
2238 3. at least one of them is plain, <<
2239 <<
2240 4. they occur on different CPUs (or in d <<
2241 same CPU), and <<
2242 <<
2243 5. they execute concurrently. <<
2244 <<
2245 In the literature, two accesses are said to " <<
2246 1 and 2 above. We'll go a little farther and <<
2247 are "race candidates" if they satisfy 1 - 4. <<
2248 race candidates actually do race in a given e <<
2249 whether they are concurrent. <<
2250 <<
2251 The LKMM tries to determine whether a program <<
2252 which may execute concurrently; if it does th <<
2253 a potential data race and makes no prediction <<
2254 outcome. <<
2255 <<
2256 Determining whether two accesses are race can <<
2257 see that all the concepts involved in the def <<
2258 part of the memory model. The hard part is t <<
2259 execute concurrently. The LKMM takes a conse <<
2260 assuming that accesses may be concurrent unle <<
2261 are not. <<
2262 <<
2263 If two memory accesses aren't concurrent then <<
2264 the other. Therefore the LKMM decides two ac <<
2265 if they can be connected by a sequence of hb, <<
2266 (together referred to as xb, for "executes be <<
2267 are two complicating factors. <<
2268 <<
2269 If X is a load and X executes before a store <<
2270 no danger of X and Y being concurrent. After <<
2271 effect on the value obtained by X until the m <<
2272 propagated Y from its own CPU to X's CPU, whi <<
2273 some time after Y executes and thus after X e <<
2274 store, then even if X executes before Y it is <<
2275 will propagate to Y's CPU just as Y is execut <<
2276 could very well interfere somehow with Y, and <<
2277 consider X and Y to be concurrent. <<
2278 <<
2279 Therefore when X is a store, for X and Y to b <<
2280 requires not only that X must execute before <<
2281 propagate to Y's CPU before Y executes. (Or <<
2282 Y executes before X -- then Y must propagate <<
2283 executes if Y is a store.) This is expressed <<
2284 relation (vis), where X ->vis Y is defined to <<
2285 intermediate event Z such that: <<
2286 <<
2287 X is connected to Z by a possibly emp <<
2288 cumul-fence links followed by an opti <<
2289 these links are present, X and Z are <<
2290 <<
2291 and either: <<
2292 <<
2293 Z is connected to Y by a strong-fence <<
2294 possibly empty sequence of xb links, <<
2295 <<
2296 or: <<
2297 <<
2298 Z is on the same CPU as Y and is conn <<
2299 empty sequence of xb links (again, if <<
2300 means Z and Y are the same event). <<
2301 <<
2302 The motivations behind this definition are st <<
2303 <<
2304 cumul-fence memory barriers force sto <<
2305 the barrier to propagate to other CPU <<
2306 po-after the barrier. <<
2307 <<
2308 An rfe link from an event W to an eve <<
2309 from W, which certainly means that W <<
2310 R's CPU before R executed. <<
2311 <<
2312 strong-fence memory barriers force st <<
2313 the barrier, or that propagate to the <<
2314 barrier executes, to propagate to all <<
2315 po-after the barrier can execute. <<
2316 <<
2317 To see how this works out in practice, consid <<
2318 pattern (with fences and statement labels, bu <<
2319 test): <<
2320 <<
2321 int buf = 0, flag = 0; <<
2322 <<
2323 P0() <<
2324 { <<
2325 X: WRITE_ONCE(buf, 1); <<
2326 smp_wmb(); <<
2327 W: WRITE_ONCE(flag, 1); <<
2328 } <<
2329 <<
2330 P1() <<
2331 { <<
2332 int r1; <<
2333 int r2 = 0; <<
2334 <<
2335 Z: r1 = READ_ONCE(flag); <<
2336 smp_rmb(); <<
2337 Y: r2 = READ_ONCE(buf); <<
2338 } <<
2339 <<
2340 The smp_wmb() memory barrier gives a cumul-fe <<
2341 assuming r1 = 1 at the end, there is an rfe l <<
2342 means that the store to buf must propagate fr <<
2343 executes. Next, Z and Y are on the same CPU <<
2344 provides an xb link from Z to Y (i.e., it for <<
2345 Y). Therefore we have X ->vis Y: X must prop <<
2346 executes. <<
2347 <<
2348 The second complicating factor mentioned abov <<
2349 that when we are considering data races, some <<
2350 are plain. Now, although we have not said so <<
2351 point most of the relations defined by the LK <<
2352 cumul-fence, pb, and so on -- including vis) <<
2353 accesses. <<
2354 <<
2355 There are good reasons for this restriction. <<
2356 allowed to apply fancy transformations to mar <<
2357 consequently each such access in the source c <<
2358 less directly to a single machine instruction <<
2359 plain accesses are a different story; the com <<
2360 split them up, duplicate them, eliminate them <<
2361 who knows what else. Seeing a plain access i <<
2362 you almost nothing about what machine instruc <<
2363 object code. <<
2364 <<
2365 Fortunately, the compiler isn't completely fr <<
2366 limitations. For one, it is not allowed to i <<
2367 the object code if the source code does not a <<
2368 race (if it could, memory models would be use <<
2369 code would be safe!). For another, it cannot <<
2370 a compiler barrier. <<
2371 <<
2372 A compiler barrier is a kind of fence, but as <<
2373 only affects the compiler; it does not necess <<
2374 how instructions are executed by the CPU. In <<
2375 code, the barrier() function is a compiler ba <<
2376 rise directly to any machine instructions in <<
2377 it affects how the compiler generates the res <<
2378 Given source code like this: <<
2379 <<
2380 ... some memory accesses ... <<
2381 barrier(); <<
2382 ... some other memory accesses ... <<
2383 <<
2384 the barrier() function ensures that the machi <<
2385 corresponding to the first group of accesses <<
2386 any machine instructions corresponding to the <<
2387 -- even if some of the accesses are plain. ( <<
2388 then execute some of those accesses out of pr <<
2389 already know how to deal with such issues.) <<
2390 there would be no such guarantee; the two gro <<
2391 intermingled or even reversed in the object c <<
2392 <<
2393 The LKMM doesn't say much about the barrier() <<
2394 require that all fences are also compiler bar <<
2395 requires that the ordering properties of memo <<
2396 smp_rmb() or smp_store_release() apply to pla <<
2397 marked accesses. <<
2398 <<
2399 This is the key to analyzing data races. Con <<
2400 again, now using plain accesses for buf: <<
2401 <<
2402 int buf = 0, flag = 0; <<
2403 <<
2404 P0() <<
2405 { <<
2406 U: buf = 1; <<
2407 smp_wmb(); <<
2408 X: WRITE_ONCE(flag, 1); <<
2409 } <<
2410 <<
2411 P1() <<
2412 { <<
2413 int r1; <<
2414 int r2 = 0; <<
2415 <<
2416 Y: r1 = READ_ONCE(flag); <<
2417 if (r1) { <<
2418 smp_rmb(); <<
2419 V: r2 = buf; <<
2420 } <<
2421 } <<
2422 <<
2423 This program does not contain a data race. A <<
2424 accesses are race candidates, the LKMM can pr <<
2425 concurrent as follows: <<
2426 <<
2427 The smp_wmb() fence in P0 is both a c <<
2428 cumul-fence. It guarantees that no m <<
2429 machine instructions the compiler gen <<
2430 access U, all those instructions will <<
2431 Consequently U's store to buf, no mat <<
2432 at the machine level, must propagate <<
2433 flag does. <<
2434 <<
2435 X and Y are both marked accesses. He <<
2436 Y is a valid indicator that X propaga <<
2437 executed, i.e., X ->vis Y. (And if t <<
2438 r1 will be 0, so V will not be execut <<
2439 race with U.) <<
2440 <<
2441 The smp_rmb() fence in P1 is a compil <<
2442 fence. It guarantees that all the ma <<
2443 corresponding to the access V will be <<
2444 therefore any loads among those instr <<
2445 after the fence does and hence after <<
2446 <<
2447 Thus U's store to buf is forced to propagate <<
2448 executes (assuming V does execute), ruling ou <<
2449 data race between them. <<
2450 <<
2451 This analysis illustrates how the LKMM deals <<
2452 general. Suppose R is a plain load and we wa <<
2453 executes before some marked access E. We can <<
2454 marked access X such that R and X are ordered <<
2455 X ->xb* E. If E was also a plain access, we <<
2456 marked access Y such that X ->xb* Y, and Y an <<
2457 fence. We describe this arrangement by sayin <<
2458 "post-bounded" by X and E is "pre-bounded" by <<
2459 <<
2460 In fact, we go one step further: Since R is a <<
2461 "r-post-bounded" by X. Similarly, E would be <<
2462 "w-pre-bounded" by Y, depending on whether E <<
2463 This distinction is needed because some fence <<
2464 (i.e., smp_rmb()) and some affect only stores <<
2465 the two types of bounds are the same. And as <<
2466 say that a marked access pre-bounds and post- <<
2467 above were a marked load then X could simply <<
2468 <<
2469 The need to distinguish between r- and w-boun <<
2470 issue. When the source code contains a plain <<
2471 allowed to put plain loads of the same locati <<
2472 For example, given the source code: <<
2473 <<
2474 x = 1; <<
2475 <<
2476 the compiler is theoretically allowed to gene <<
2477 looks like: <<
2478 <<
2479 if (x != 1) <<
2480 x = 1; <<
2481 <<
2482 thereby adding a load (and possibly replacing <<
2483 For this reason, whenever the LKMM requires a <<
2484 w-pre-bounded or w-post-bounded by a marked a <<
2485 the store to be r-pre-bounded or r-post-bound <<
2486 where the compiler adds a load. <<
2487 <<
2488 (This may be overly cautious. We don't know <<
2489 compiler has augmented a store with a load in <<
2490 Linux kernel developers would probably fight <<
2491 compiler if it ever did this. Still, better <<
2492 <<
2493 Incidentally, the other tranformation -- augm <<
2494 adding in a store to the same location -- is <<
2495 because the compiler cannot know whether any <<
2496 a concurrent load from that location. Two co <<
2497 constitute a race (they can't interfere with <<
2498 does race with a concurrent load. Thus addin <<
2499 data race where one was not already present i <<
2500 something the compiler is forbidden to do. A <<
2501 load, on the other hand, is acceptable becaus <<
2502 data race unless one already existed. <<
2503 <<
2504 The LKMM includes a second way to pre-bound p <<
2505 addition to fences: an address dependency fro <<
2506 is, in the sequence: <<
2507 <<
2508 p = READ_ONCE(ptr); <<
2509 r = *p; <<
2510 <<
2511 the LKMM says that the marked load of ptr pre <<
2512 *p; the marked load must execute before any o <<
2513 instructions corresponding to the plain load. <<
2514 stipulation, since after all, the CPU can't p <<
2515 until it knows what value p will hold. Furth <<
2516 assumption like this one, some usages typical <<
2517 data races. For example: <<
2518 <<
2519 int a = 1, b; <<
2520 int *ptr = &a; <<
2521 <<
2522 P0() <<
2523 { <<
2524 b = 2; <<
2525 rcu_assign_pointer(ptr, &b); <<
2526 } <<
2527 <<
2528 P1() <<
2529 { <<
2530 int *p; <<
2531 int r; <<
2532 <<
2533 rcu_read_lock(); <<
2534 p = rcu_dereference(ptr); <<
2535 r = *p; <<
2536 rcu_read_unlock(); <<
2537 } <<
2538 <<
2539 (In this example the rcu_read_lock() and rcu_ <<
2540 really do anything, because there aren't any <<
2541 included merely for the sake of good form; ty <<
2542 synchronize_rcu() somewhere after the rcu_ass <<
2543 <<
2544 rcu_assign_pointer() performs a store-release <<
2545 is definitely w-post-bounded before the store <<
2546 stores will propagate to P1 in that order. H <<
2547 is only equivalent to READ_ONCE(). While it <<
2548 not a fence or compiler barrier. Hence the o <<
2549 that the load of ptr in P1 is r-pre-bounded b <<
2550 (thus avoiding a race) is the assumption abou <<
2551 <<
2552 This is a situation where the compiler can un <<
2553 and a certain amount of care is required when <<
2554 like this one. In particular, comparisons be <<
2555 other known addresses can cause trouble. If <<
2556 <<
2557 p = rcu_dereference(ptr); <<
2558 if (p == &x) <<
2559 r = *p; <<
2560 <<
2561 then the compiler just might generate object <<
2562 <<
2563 p = rcu_dereference(ptr); <<
2564 if (p == &x) <<
2565 r = x; <<
2566 <<
2567 or even: <<
2568 <<
2569 rtemp = x; <<
2570 p = rcu_dereference(ptr); <<
2571 if (p == &x) <<
2572 r = rtemp; <<
2573 <<
2574 which would invalidate the memory model's ass <<
2575 could now perform the load of x before the lo <<
2576 a control dependency but no address dependenc <<
2577 <<
2578 Finally, it turns out there is a situation in <<
2579 not need to be w-post-bounded: when it is sep <<
2580 race-candidate access by a fence. At first g <<
2581 impossible. After all, to be race candidates <<
2582 be on different CPUs, and fences don't link e <<
2583 Well, normal fences don't -- but rcu-fence ca <<
2584 <<
2585 int x, y; <<
2586 <<
2587 P0() <<
2588 { <<
2589 WRITE_ONCE(x, 1); <<
2590 synchronize_rcu(); <<
2591 y = 3; <<
2592 } <<
2593 <<
2594 P1() <<
2595 { <<
2596 rcu_read_lock(); <<
2597 if (READ_ONCE(x) == 0) <<
2598 y = 2; <<
2599 rcu_read_unlock(); <<
2600 } <<
2601 <<
2602 Do the plain stores to y race? Clearly not i <<
2603 value for x, so let's assume the READ_ONCE(x) <<
2604 means that the read-side critical section in <<
2605 before the grace period in P0 does, because R <<
2606 Guarantee says that otherwise P0's store to x <<
2607 P1 before the critical section started and so <<
2608 to the READ_ONCE(). (Another way of putting <<
2609 from the READ_ONCE() to the WRITE_ONCE() give <<
2610 between those two events.) <<
2611 <<
2612 This means there is an rcu-fence link from P1 <<
2613 "y = 3" store, and consequently the first mus <<
2614 before the second can execute. Therefore the <<
2615 concurrent and there is no race, even though <<
2616 isn't w-post-bounded by any marked accesses. <<
2617 <<
2618 Putting all this material together yields the <<
2619 race-candidate stores W and W', where W ->co <<
2620 stores don't race if W can be linked to W' by <<
2621 <<
2622 w-post-bounded ; vis ; w-pre-bounded <<
2623 <<
2624 sequence. If W is plain then they also have <<
2625 <<
2626 r-post-bounded ; xb* ; w-pre-bounded <<
2627 <<
2628 sequence, and if W' is plain then they also h <<
2629 <<
2630 w-post-bounded ; vis ; r-pre-bounded <<
2631 <<
2632 sequence. For race-candidate load R and stor <<
2633 two accesses don't race if R can be linked to <<
2634 <<
2635 r-post-bounded ; xb* ; w-pre-bounded <<
2636 <<
2637 sequence or if W can be linked to R by a <<
2638 <<
2639 w-post-bounded ; vis ; r-pre-bounded <<
2640 <<
2641 sequence. For the cases involving a vis link <<
2642 sequences in which W is linked to W' or R by <<
2643 <<
2644 strong-fence ; xb* ; {w and/or r}-pre <<
2645 <<
2646 sequence with no post-bounding, and in every <<
2647 the link simply to be a fence with no boundin <<
2648 of the appropriate sort exists, the LKMM says <<
2649 <<
2650 There is one more part of the LKMM related to <<
2651 not to data races) we should discuss. Recall <<
2652 as hb are limited to marked accesses only. A <<
2653 happens-before, propagates-before, and rcu ax <<
2654 various relation must not contain a cycle) do <<
2655 accesses. Nevertheless, we do want to rule o <<
2656 they don't make sense even for plain accesses <<
2657 <<
2658 To this end, the LKMM imposes three extra res <<
2659 called the "plain-coherence" axiom because of <<
2660 rules used by the operational model to ensure <<
2661 is, the rules governing the memory subsystem' <<
2662 satisfy a load request and its determination <<
2663 fall in the coherence order): <<
2664 <<
2665 If R and W are race candidates and it <<
2666 W by one of the xb* sequences listed <<
2667 not allowed (i.e., a load cannot read <<
2668 executes before, even if one or both <<
2669 <<
2670 If W and R are race candidates and it <<
2671 R by one of the vis sequences listed <<
2672 not allowed (i.e., if a store is visi <<
2673 load must read from that store or one <<
2674 <<
2675 If W and W' are race candidates and i <<
2676 to W' by one of the vis sequences lis <<
2677 is not allowed (i.e., if one store is <<
2678 the second must come after the first <<
2679 <<
2680 This is the extent to which the LKMM deals wi <<
2681 Perhaps it could say more (for example, plain <<
2682 contribute to the ppo relation), but at the m <<
2683 minimal, conservative approach is good enough <<
2684 <<
2685 <<
2686 ODDS AND ENDS 1889 ODDS AND ENDS
2687 ------------- 1890 -------------
2688 1891
2689 This section covers material that didn't quit 1892 This section covers material that didn't quite fit anywhere in the
2690 earlier sections. 1893 earlier sections.
2691 1894
2692 The descriptions in this document don't alway 1895 The descriptions in this document don't always match the formal
2693 version of the LKMM exactly. For example, th 1896 version of the LKMM exactly. For example, the actual formal
2694 definition of the prop relation makes the ini 1897 definition of the prop relation makes the initial coe or fre part
2695 optional, and it doesn't require the events l 1898 optional, and it doesn't require the events linked by the relation to
2696 be on the same CPU. These differences are ve 1899 be on the same CPU. These differences are very unimportant; indeed,
2697 instances where the coe/fre part of prop is m 1900 instances where the coe/fre part of prop is missing are of no interest
2698 because all the other parts (fences and rfe) 1901 because all the other parts (fences and rfe) are already included in
2699 hb anyway, and where the formal model adds pr 1902 hb anyway, and where the formal model adds prop into hb, it includes
2700 an explicit requirement that the events being 1903 an explicit requirement that the events being linked are on the same
2701 CPU. 1904 CPU.
2702 1905
2703 Another minor difference has to do with event 1906 Another minor difference has to do with events that are both memory
2704 accesses and fences, such as those correspond 1907 accesses and fences, such as those corresponding to smp_load_acquire()
2705 calls. In the formal model, these events are 1908 calls. In the formal model, these events aren't actually both reads
2706 and fences; rather, they are read events with 1909 and fences; rather, they are read events with an annotation marking
2707 them as acquires. (Or write events annotated 1910 them as acquires. (Or write events annotated as releases, in the case
2708 smp_store_release().) The final effect is th 1911 smp_store_release().) The final effect is the same.
2709 1912
2710 Although we didn't mention it above, the inst 1913 Although we didn't mention it above, the instruction execution
2711 ordering provided by the smp_rmb() fence does 1914 ordering provided by the smp_rmb() fence doesn't apply to read events
2712 that are part of a non-value-returning atomic 1915 that are part of a non-value-returning atomic update. For instance,
2713 given: 1916 given:
2714 1917
2715 atomic_inc(&x); 1918 atomic_inc(&x);
2716 smp_rmb(); 1919 smp_rmb();
2717 r1 = READ_ONCE(y); 1920 r1 = READ_ONCE(y);
2718 1921
2719 it is not guaranteed that the load from y wil 1922 it is not guaranteed that the load from y will execute after the
2720 update to x. This is because the ARMv8 archi 1923 update to x. This is because the ARMv8 architecture allows
2721 non-value-returning atomic operations effecti 1924 non-value-returning atomic operations effectively to be executed off
2722 the CPU. Basically, the CPU tells the memory 1925 the CPU. Basically, the CPU tells the memory subsystem to increment
2723 x, and then the increment is carried out by t 1926 x, and then the increment is carried out by the memory hardware with
2724 no further involvement from the CPU. Since t 1927 no further involvement from the CPU. Since the CPU doesn't ever read
2725 the value of x, there is nothing for the smp_ 1928 the value of x, there is nothing for the smp_rmb() fence to act on.
2726 1929
2727 The LKMM defines a few extra synchronization 1930 The LKMM defines a few extra synchronization operations in terms of
2728 things we have already covered. In particula 1931 things we have already covered. In particular, rcu_dereference() is
2729 treated as READ_ONCE() and rcu_assign_pointer 1932 treated as READ_ONCE() and rcu_assign_pointer() is treated as
2730 smp_store_release() -- which is basically how 1933 smp_store_release() -- which is basically how the Linux kernel treats
2731 them. 1934 them.
2732 1935
2733 Although we said that plain accesses are not <<
2734 relation, they do contribute to it indirectly <<
2735 an address dependency from a marked load R to <<
2736 followed by smp_wmb() and then a marked store <<
2737 ppo link from R to W'. The reasoning behind <<
2738 shaky, but essentially it says there is no wa <<
2739 for this source code in which W' could execut <<
2740 pre-bounding by address dependencies, it is p <<
2741 to undermine this relation if sufficient care <<
2742 <<
2743 Secondly, plain accesses can carry dependenci <<
2744 links a marked load R to a store W, and the s <<
2745 from the same thread, then the data loaded by <<
2746 loaded originally by R. Thus, if R' is linked <<
2747 dependency, R is also linked to access X by t <<
2748 if W' or R' (or both!) are plain. <<
2749 <<
2750 There are a few oddball fences which need spe 1936 There are a few oddball fences which need special treatment:
2751 smp_mb__before_atomic(), smp_mb__after_atomic 1937 smp_mb__before_atomic(), smp_mb__after_atomic(), and
2752 smp_mb__after_spinlock(). The LKMM uses fenc 1938 smp_mb__after_spinlock(). The LKMM uses fence events with special
2753 annotations for them; they act as strong fenc 1939 annotations for them; they act as strong fences just like smp_mb()
2754 except for the sets of events that they order 1940 except for the sets of events that they order. Instead of ordering
2755 all po-earlier events against all po-later ev 1941 all po-earlier events against all po-later events, as smp_mb() does,
2756 they behave as follows: 1942 they behave as follows:
2757 1943
2758 smp_mb__before_atomic() orders all po 1944 smp_mb__before_atomic() orders all po-earlier events against
2759 po-later atomic updates and the event 1945 po-later atomic updates and the events following them;
2760 1946
2761 smp_mb__after_atomic() orders po-earl 1947 smp_mb__after_atomic() orders po-earlier atomic updates and
2762 the events preceding them against all 1948 the events preceding them against all po-later events;
2763 1949
2764 smp_mb__after_spinlock() orders po-ea !! 1950 smp_mb_after_spinlock() orders po-earlier lock acquisition
2765 events and the events preceding them 1951 events and the events preceding them against all po-later
2766 events. 1952 events.
2767 1953
2768 Interestingly, RCU and locking each introduce 1954 Interestingly, RCU and locking each introduce the possibility of
2769 deadlock. When faced with code sequences suc 1955 deadlock. When faced with code sequences such as:
2770 1956
2771 spin_lock(&s); 1957 spin_lock(&s);
2772 spin_lock(&s); 1958 spin_lock(&s);
2773 spin_unlock(&s); 1959 spin_unlock(&s);
2774 spin_unlock(&s); 1960 spin_unlock(&s);
2775 1961
2776 or: 1962 or:
2777 1963
2778 rcu_read_lock(); 1964 rcu_read_lock();
2779 synchronize_rcu(); 1965 synchronize_rcu();
2780 rcu_read_unlock(); 1966 rcu_read_unlock();
2781 1967
2782 what does the LKMM have to say? Answer: It s 1968 what does the LKMM have to say? Answer: It says there are no allowed
2783 executions at all, which makes sense. But th 1969 executions at all, which makes sense. But this can also lead to
2784 misleading results, because if a piece of cod 1970 misleading results, because if a piece of code has multiple possible
2785 executions, some of which deadlock, the model 1971 executions, some of which deadlock, the model will report only on the
2786 non-deadlocking executions. For example: 1972 non-deadlocking executions. For example:
2787 1973
2788 int x, y; 1974 int x, y;
2789 1975
2790 P0() 1976 P0()
2791 { 1977 {
2792 int r0; 1978 int r0;
2793 1979
2794 WRITE_ONCE(x, 1); 1980 WRITE_ONCE(x, 1);
2795 r0 = READ_ONCE(y); 1981 r0 = READ_ONCE(y);
2796 } 1982 }
2797 1983
2798 P1() 1984 P1()
2799 { 1985 {
2800 rcu_read_lock(); 1986 rcu_read_lock();
2801 if (READ_ONCE(x) > 0) { 1987 if (READ_ONCE(x) > 0) {
2802 WRITE_ONCE(y, 36); 1988 WRITE_ONCE(y, 36);
2803 synchronize_rcu(); 1989 synchronize_rcu();
2804 } 1990 }
2805 rcu_read_unlock(); 1991 rcu_read_unlock();
2806 } 1992 }
2807 1993
2808 Is it possible to end up with r0 = 36 at the 1994 Is it possible to end up with r0 = 36 at the end? The LKMM will tell
2809 you it is not, but the model won't mention th 1995 you it is not, but the model won't mention that this is because P1
2810 will self-deadlock in the executions where it 1996 will self-deadlock in the executions where it stores 36 in y.
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