1 perf-c2c(1) 1 perf-c2c(1)
2 =========== 2 ===========
3 3
4 NAME 4 NAME
5 ---- 5 ----
6 perf-c2c - Shared Data C2C/HITM Analyzer. 6 perf-c2c - Shared Data C2C/HITM Analyzer.
7 7
8 SYNOPSIS 8 SYNOPSIS
9 -------- 9 --------
10 [verse] 10 [verse]
11 'perf c2c record' [<options>] <command> 11 'perf c2c record' [<options>] <command>
12 'perf c2c record' [<options>] \-- [<record com !! 12 'perf c2c record' [<options>] -- [<record command options>] <command>
13 'perf c2c report' [<options>] 13 'perf c2c report' [<options>]
14 14
15 DESCRIPTION 15 DESCRIPTION
16 ----------- 16 -----------
17 C2C stands for Cache To Cache. 17 C2C stands for Cache To Cache.
18 18
19 The perf c2c tool provides means for Shared Da 19 The perf c2c tool provides means for Shared Data C2C/HITM analysis. It allows
20 you to track down the cacheline contentions. 20 you to track down the cacheline contentions.
21 21
22 On Intel, the tool is based on load latency an !! 22 The tool is based on x86's load latency and precise store facility events
23 provided by Intel CPUs. On PowerPC, the tool u !! 23 provided by Intel CPUs. These events provide:
24 with thresholding feature. On AMD, the tool us <<
25 limitations, perf c2c is not supported on Zen3 <<
26 sample load and store operations, therefore ha <<
27 required. See linkperf:perf-arm-spe[1] for a s <<
28 statistical nature of Arm SPE sampling, not ev <<
29 sampled. <<
30 <<
31 These events provide: <<
32 - memory address of the access 24 - memory address of the access
33 - type of the access (load and store details 25 - type of the access (load and store details)
34 - latency (in cycles) of the load access 26 - latency (in cycles) of the load access
35 27
36 The c2c tool provide means to record this data 28 The c2c tool provide means to record this data and report back access details
37 for cachelines with highest contention - highe 29 for cachelines with highest contention - highest number of HITM accesses.
38 30
39 The basic workflow with this tool follows the 31 The basic workflow with this tool follows the standard record/report phase.
40 User uses the record command to record events 32 User uses the record command to record events data and report command to
41 display it. 33 display it.
42 34
43 35
44 RECORD OPTIONS 36 RECORD OPTIONS
45 -------------- 37 --------------
46 -e:: 38 -e::
47 --event=:: 39 --event=::
48 Select the PMU event. Use 'perf c2c re !! 40 Select the PMU event. Use 'perf mem record -e list'
49 to list available events. 41 to list available events.
50 42
51 -v:: 43 -v::
52 --verbose:: 44 --verbose::
53 Be more verbose (show counter open err 45 Be more verbose (show counter open errors, etc).
54 46
55 -l:: 47 -l::
56 --ldlat:: 48 --ldlat::
57 Configure mem-loads latency. Supported !! 49 Configure mem-loads latency.
58 only. Ignored on other archs. <<
59 50
60 -k:: 51 -k::
61 --all-kernel:: 52 --all-kernel::
62 Configure all used events to run in ke 53 Configure all used events to run in kernel space.
63 54
64 -u:: 55 -u::
65 --all-user:: 56 --all-user::
66 Configure all used events to run in us 57 Configure all used events to run in user space.
67 58
68 REPORT OPTIONS 59 REPORT OPTIONS
69 -------------- 60 --------------
70 -k:: 61 -k::
71 --vmlinux=<file>:: 62 --vmlinux=<file>::
72 vmlinux pathname 63 vmlinux pathname
73 64
74 -v:: 65 -v::
75 --verbose:: 66 --verbose::
76 Be more verbose (show counter open err 67 Be more verbose (show counter open errors, etc).
77 68
78 -i:: 69 -i::
79 --input:: 70 --input::
80 Specify the input file to process. 71 Specify the input file to process.
81 72
82 -N:: 73 -N::
83 --node-info:: 74 --node-info::
84 Show extra node info in report (see NO 75 Show extra node info in report (see NODE INFO section)
85 76
86 -c:: 77 -c::
87 --coalesce:: 78 --coalesce::
88 Specify sorting fields for single cach 79 Specify sorting fields for single cacheline display.
89 Following fields are available: tid,pi 80 Following fields are available: tid,pid,iaddr,dso
90 (see COALESCE) 81 (see COALESCE)
91 82
92 -g:: 83 -g::
93 --call-graph:: 84 --call-graph::
94 Setup callchains parameters. 85 Setup callchains parameters.
95 Please refer to perf-report man page f 86 Please refer to perf-report man page for details.
96 87
97 --stdio:: 88 --stdio::
98 Force the stdio output (see STDIO OUTP 89 Force the stdio output (see STDIO OUTPUT)
99 90
100 --stats:: 91 --stats::
101 Display only statistic tables and forc 92 Display only statistic tables and force stdio mode.
102 93
103 --full-symbols:: 94 --full-symbols::
104 Display full length of symbols. 95 Display full length of symbols.
105 96
106 --no-source:: 97 --no-source::
107 Do not display Source:Line column. 98 Do not display Source:Line column.
108 99
109 --show-all:: 100 --show-all::
110 Show all captured HITM lines, with no 101 Show all captured HITM lines, with no regard to HITM % 0.0005 limit.
111 102
112 -f:: 103 -f::
113 --force:: 104 --force::
114 Don't do ownership validation. 105 Don't do ownership validation.
115 106
116 -d:: 107 -d::
117 --display:: 108 --display::
118 Switch to HITM type (rmt, lcl) or peer !! 109 Switch to HITM type (rmt, lcl) to display and sort on. Total HITMs as default.
119 and sort on. Total HITMs (tot) as defa <<
120 as default. <<
121 <<
122 --stitch-lbr:: <<
123 Show callgraph with stitched LBRs, whi <<
124 callgraph. The perf.data file must hav <<
125 perf c2c record --call-graph lbr. <<
126 Disabled by default. In common cases w <<
127 it can recreate better call stacks tha <<
128 output. But this approach is not foolp <<
129 where it creates incorrect call stacks <<
130 The known limitations include exceptio <<
131 setjmp/longjmp will have calls/returns <<
132 <<
133 --double-cl:: <<
134 Group the detection of shared cachelin <<
135 granularity. Some architectures have a <<
136 feature, which causes cacheline sharin <<
137 size is doubled. <<
138 110
139 C2C RECORD 111 C2C RECORD
140 ---------- 112 ----------
141 The perf c2c record command setup options rela 113 The perf c2c record command setup options related to HITM cacheline analysis
142 and calls standard perf record command. 114 and calls standard perf record command.
143 115
144 Following perf record options are configured b 116 Following perf record options are configured by default:
145 (check perf record man page for details) 117 (check perf record man page for details)
146 118
147 -W,-d,--phys-data,--sample-cpu !! 119 -W,-d,--sample-cpu
148 120
149 Unless specified otherwise with '-e' option, f 121 Unless specified otherwise with '-e' option, following events are monitored by
150 default on Intel: !! 122 default:
151 123
152 cpu/mem-loads,ldlat=30/P 124 cpu/mem-loads,ldlat=30/P
153 cpu/mem-stores/P 125 cpu/mem-stores/P
154 126
155 following on AMD: <<
156 <<
157 ibs_op// <<
158 <<
159 and following on PowerPC: <<
160 <<
161 cpu/mem-loads/ <<
162 cpu/mem-stores/ <<
163 <<
164 User can pass any 'perf record' option behind 127 User can pass any 'perf record' option behind '--' mark, like (to enable
165 callchains and system wide monitoring): 128 callchains and system wide monitoring):
166 129
167 $ perf c2c record -- -g -a 130 $ perf c2c record -- -g -a
168 131
169 Please check RECORD OPTIONS section for specif 132 Please check RECORD OPTIONS section for specific c2c record options.
170 133
171 C2C REPORT 134 C2C REPORT
172 ---------- 135 ----------
173 The perf c2c report command displays shared da 136 The perf c2c report command displays shared data analysis. It comes in two
174 display modes: stdio and tui (default). 137 display modes: stdio and tui (default).
175 138
176 The report command workflow is following: 139 The report command workflow is following:
177 - sort all the data based on the cacheline a 140 - sort all the data based on the cacheline address
178 - store access details for each cacheline 141 - store access details for each cacheline
179 - sort all cachelines based on user settings 142 - sort all cachelines based on user settings
180 - display data 143 - display data
181 144
182 In general perf report output consist of 2 bas 145 In general perf report output consist of 2 basic views:
183 1) most expensive cachelines list 146 1) most expensive cachelines list
184 2) offsets details for each cacheline 147 2) offsets details for each cacheline
185 148
186 For each cacheline in the 1) list we display f 149 For each cacheline in the 1) list we display following data:
187 (Both stdio and TUI modes follow the same fiel 150 (Both stdio and TUI modes follow the same fields output)
188 151
189 Index 152 Index
190 - zero based index to identify the cacheline 153 - zero based index to identify the cacheline
191 154
192 Cacheline 155 Cacheline
193 - cacheline address (hex number) 156 - cacheline address (hex number)
194 157
195 Rmt/Lcl Hitm (Display with HITM types) !! 158 Total records
196 - cacheline percentage of all Remote/Local H !! 159 - sum of all cachelines accesses
197 160
198 Peer Snoop (Display with peer type) !! 161 Rmt/Lcl Hitm
199 - cacheline percentage of all peer accesses !! 162 - cacheline percentage of all Remote/Local HITM accesses
200 163
201 LLC Load Hitm - Total, LclHitm, RmtHitm (For !! 164 LLC Load Hitm - Total, Lcl, Rmt
202 - count of Total/Local/Remote load HITMs 165 - count of Total/Local/Remote load HITMs
203 166
204 Load Peer - Total, Local, Remote (For displa !! 167 Store Reference - Total, L1Hit, L1Miss
205 - count of Total/Local/Remote load from peer !! 168 Total - all store accesses
206 !! 169 L1Hit - store accesses that hit L1
207 Total records !! 170 L1Hit - store accesses that missed L1
208 - sum of all cachelines accesses <<
209 171
210 Total loads !! 172 Load Dram
211 - sum of all load accesses !! 173 - count of local and remote DRAM accesses
212 174
213 Total stores !! 175 LLC Ld Miss
214 - sum of all store accesses !! 176 - count of all accesses that missed LLC
215 177
216 Store Reference - L1Hit, L1Miss, N/A !! 178 Total Loads
217 L1Hit - store accesses that hit L1 !! 179 - sum of all load accesses
218 L1Miss - store accesses that missed L1 <<
219 N/A - store accesses with memory level is <<
220 180
221 Core Load Hit - FB, L1, L2 181 Core Load Hit - FB, L1, L2
222 - count of load hits in FB (Fill Buffer), L1 182 - count of load hits in FB (Fill Buffer), L1 and L2 cache
223 183
224 LLC Load Hit - LlcHit, LclHitm !! 184 LLC Load Hit - Llc, Rmt
225 - count of LLC load accesses, includes LLC h !! 185 - count of LLC and Remote load hits
226 <<
227 RMT Load Hit - RmtHit, RmtHitm <<
228 - count of remote load accesses, includes re <<
229 on Arm neoverse cores, RmtHit is used to a <<
230 includes remote DRAM or any upward cache l <<
231 <<
232 Load Dram - Lcl, Rmt <<
233 - count of local and remote DRAM accesses <<
234 186
235 For each offset in the 2) list we display foll 187 For each offset in the 2) list we display following data:
236 188
237 HITM - Rmt, Lcl (Display with HITM types) !! 189 HITM - Rmt, Lcl
238 - % of Remote/Local HITM accesses for given 190 - % of Remote/Local HITM accesses for given offset within cacheline
239 191
240 Peer Snoop - Rmt, Lcl (Display with peer typ !! 192 Store Refs - L1 Hit, L1 Miss
241 - % of Remote/Local peer accesses for given !! 193 - % of store accesses that hit/missed L1 for given offset within cacheline
242 <<
243 Store Refs - L1 Hit, L1 Miss, N/A <<
244 - % of store accesses that hit L1, missed L1 <<
245 level for given offset within cacheline <<
246 194
247 Data address - Offset 195 Data address - Offset
248 - offset address 196 - offset address
249 197
250 Pid 198 Pid
251 - pid of the process responsible for the acc 199 - pid of the process responsible for the accesses
252 200
253 Tid 201 Tid
254 - tid of the process responsible for the acc 202 - tid of the process responsible for the accesses
255 203
256 Code address 204 Code address
257 - code address responsible for the accesses 205 - code address responsible for the accesses
258 206
259 cycles - rmt hitm, lcl hitm, load (Display w !! 207 cycles - rmt hitm, lcl hitm, load
260 - sum of cycles for given accesses - Remot 208 - sum of cycles for given accesses - Remote/Local HITM and generic load
261 209
262 cycles - rmt peer, lcl peer, load (Display w <<
263 - sum of cycles for given accesses - Remot <<
264 <<
265 cpu cnt 210 cpu cnt
266 - number of cpus that participated on the 211 - number of cpus that participated on the access
267 212
268 Symbol 213 Symbol
269 - code symbol related to the 'Code address 214 - code symbol related to the 'Code address' value
270 215
271 Shared Object 216 Shared Object
272 - shared object name related to the 'Code 217 - shared object name related to the 'Code address' value
273 218
274 Source:Line 219 Source:Line
275 - source information related to the 'Code 220 - source information related to the 'Code address' value
276 221
277 Node 222 Node
278 - nodes participating on the access (see N 223 - nodes participating on the access (see NODE INFO section)
279 224
280 NODE INFO 225 NODE INFO
281 --------- 226 ---------
282 The 'Node' field displays nodes that accesses 227 The 'Node' field displays nodes that accesses given cacheline
283 offset. Its output comes in 3 flavors: 228 offset. Its output comes in 3 flavors:
284 - node IDs separated by ',' 229 - node IDs separated by ','
285 - node IDs with stats for each ID, in follow 230 - node IDs with stats for each ID, in following format:
286 Node{cpus %hitms %stores} (Display with !! 231 Node{cpus %hitms %stores}
287 Node{cpus %peers %stores} (Display with <<
288 - node IDs with list of affected CPUs in fol 232 - node IDs with list of affected CPUs in following format:
289 Node{cpu list} 233 Node{cpu list}
290 234
291 User can switch between above flavors with -N 235 User can switch between above flavors with -N option or
292 use 'n' key to interactively switch in TUI mod 236 use 'n' key to interactively switch in TUI mode.
293 237
294 COALESCE 238 COALESCE
295 -------- 239 --------
296 User can specify how to sort offsets for cache 240 User can specify how to sort offsets for cacheline.
297 241
298 Following fields are available and governs the 242 Following fields are available and governs the final
299 output fields set for cacheline offsets output !! 243 output fields set for caheline offsets output:
300 244
301 tid - coalesced by process TIDs 245 tid - coalesced by process TIDs
302 pid - coalesced by process PIDs 246 pid - coalesced by process PIDs
303 iaddr - coalesced by code address, following 247 iaddr - coalesced by code address, following fields are displayed:
304 Code address, Code symbol, Shared 248 Code address, Code symbol, Shared Object, Source line
305 dso - coalesced by shared object 249 dso - coalesced by shared object
306 250
307 By default the coalescing is setup with 'pid,i 251 By default the coalescing is setup with 'pid,iaddr'.
308 252
309 STDIO OUTPUT 253 STDIO OUTPUT
310 ------------ 254 ------------
311 The stdio output displays data on standard out 255 The stdio output displays data on standard output.
312 256
313 Following tables are displayed: 257 Following tables are displayed:
314 Trace Event Information 258 Trace Event Information
315 - overall statistics of memory accesses 259 - overall statistics of memory accesses
316 260
317 Global Shared Cache Line Event Information 261 Global Shared Cache Line Event Information
318 - overall statistics on shared cachelines 262 - overall statistics on shared cachelines
319 263
320 Shared Data Cache Line Table 264 Shared Data Cache Line Table
321 - list of most expensive cachelines 265 - list of most expensive cachelines
322 266
323 Shared Cache Line Distribution Pareto 267 Shared Cache Line Distribution Pareto
324 - list of all accessed offsets for each cach 268 - list of all accessed offsets for each cacheline
325 269
326 TUI OUTPUT 270 TUI OUTPUT
327 ---------- 271 ----------
328 The TUI output provides interactive interface 272 The TUI output provides interactive interface to navigate
329 through cachelines list and to display offset 273 through cachelines list and to display offset details.
330 274
331 For details please refer to the help window by 275 For details please refer to the help window by pressing '?' key.
332 276
333 CREDITS 277 CREDITS
334 ------- 278 -------
335 Although Don Zickus, Dick Fowles and Joe Mario 279 Although Don Zickus, Dick Fowles and Joe Mario worked together
336 to get this implemented, we got lots of early 280 to get this implemented, we got lots of early help from Arnaldo
337 Carvalho de Melo, Stephane Eranian, Jiri Olsa 281 Carvalho de Melo, Stephane Eranian, Jiri Olsa and Andi Kleen.
338 282
339 C2C BLOG 283 C2C BLOG
340 -------- 284 --------
341 Check Joe's blog on c2c tool for detailed use 285 Check Joe's blog on c2c tool for detailed use case explanation:
342 https://joemario.github.io/blog/2016/09/01/c 286 https://joemario.github.io/blog/2016/09/01/c2c-blog/
343 287
344 SEE ALSO 288 SEE ALSO
345 -------- 289 --------
346 linkperf:perf-record[1], linkperf:perf-mem[1], !! 290 linkperf:perf-record[1], linkperf:perf-mem[1]
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