1 perf-c2c(1) 1 perf-c2c(1)
2 =========== 2 ===========
3 3
4 NAME 4 NAME
5 ---- 5 ----
6 perf-c2c - Shared Data C2C/HITM Analyzer. 6 perf-c2c - Shared Data C2C/HITM Analyzer.
7 7
8 SYNOPSIS 8 SYNOPSIS
9 -------- 9 --------
10 [verse] 10 [verse]
11 'perf c2c record' [<options>] <command> 11 'perf c2c record' [<options>] <command>
12 'perf c2c record' [<options>] \-- [<record com !! 12 'perf c2c record' [<options>] -- [<record command options>] <command>
13 'perf c2c report' [<options>] 13 'perf c2c report' [<options>]
14 14
15 DESCRIPTION 15 DESCRIPTION
16 ----------- 16 -----------
17 C2C stands for Cache To Cache. 17 C2C stands for Cache To Cache.
18 18
19 The perf c2c tool provides means for Shared Da 19 The perf c2c tool provides means for Shared Data C2C/HITM analysis. It allows
20 you to track down the cacheline contentions. 20 you to track down the cacheline contentions.
21 21
22 On Intel, the tool is based on load latency an !! 22 On x86, the tool is based on load latency and precise store facility events
23 provided by Intel CPUs. On PowerPC, the tool u 23 provided by Intel CPUs. On PowerPC, the tool uses random instruction sampling
24 with thresholding feature. On AMD, the tool us !! 24 with thresholding feature.
25 limitations, perf c2c is not supported on Zen3 <<
26 sample load and store operations, therefore ha <<
27 required. See linkperf:perf-arm-spe[1] for a s <<
28 statistical nature of Arm SPE sampling, not ev <<
29 sampled. <<
30 25
31 These events provide: 26 These events provide:
32 - memory address of the access 27 - memory address of the access
33 - type of the access (load and store details 28 - type of the access (load and store details)
34 - latency (in cycles) of the load access 29 - latency (in cycles) of the load access
35 30
36 The c2c tool provide means to record this data 31 The c2c tool provide means to record this data and report back access details
37 for cachelines with highest contention - highe 32 for cachelines with highest contention - highest number of HITM accesses.
38 33
39 The basic workflow with this tool follows the 34 The basic workflow with this tool follows the standard record/report phase.
40 User uses the record command to record events 35 User uses the record command to record events data and report command to
41 display it. 36 display it.
42 37
43 38
44 RECORD OPTIONS 39 RECORD OPTIONS
45 -------------- 40 --------------
46 -e:: 41 -e::
47 --event=:: 42 --event=::
48 Select the PMU event. Use 'perf c2c re !! 43 Select the PMU event. Use 'perf mem record -e list'
49 to list available events. 44 to list available events.
50 45
51 -v:: 46 -v::
52 --verbose:: 47 --verbose::
53 Be more verbose (show counter open err 48 Be more verbose (show counter open errors, etc).
54 49
55 -l:: 50 -l::
56 --ldlat:: 51 --ldlat::
57 Configure mem-loads latency. Supported !! 52 Configure mem-loads latency. (x86 only)
58 only. Ignored on other archs. <<
59 53
60 -k:: 54 -k::
61 --all-kernel:: 55 --all-kernel::
62 Configure all used events to run in ke 56 Configure all used events to run in kernel space.
63 57
64 -u:: 58 -u::
65 --all-user:: 59 --all-user::
66 Configure all used events to run in us 60 Configure all used events to run in user space.
67 61
68 REPORT OPTIONS 62 REPORT OPTIONS
69 -------------- 63 --------------
70 -k:: 64 -k::
71 --vmlinux=<file>:: 65 --vmlinux=<file>::
72 vmlinux pathname 66 vmlinux pathname
73 67
74 -v:: 68 -v::
75 --verbose:: 69 --verbose::
76 Be more verbose (show counter open err 70 Be more verbose (show counter open errors, etc).
77 71
78 -i:: 72 -i::
79 --input:: 73 --input::
80 Specify the input file to process. 74 Specify the input file to process.
81 75
82 -N:: 76 -N::
83 --node-info:: 77 --node-info::
84 Show extra node info in report (see NO 78 Show extra node info in report (see NODE INFO section)
85 79
86 -c:: 80 -c::
87 --coalesce:: 81 --coalesce::
88 Specify sorting fields for single cach 82 Specify sorting fields for single cacheline display.
89 Following fields are available: tid,pi 83 Following fields are available: tid,pid,iaddr,dso
90 (see COALESCE) 84 (see COALESCE)
91 85
92 -g:: 86 -g::
93 --call-graph:: 87 --call-graph::
94 Setup callchains parameters. 88 Setup callchains parameters.
95 Please refer to perf-report man page f 89 Please refer to perf-report man page for details.
96 90
97 --stdio:: 91 --stdio::
98 Force the stdio output (see STDIO OUTP 92 Force the stdio output (see STDIO OUTPUT)
99 93
100 --stats:: 94 --stats::
101 Display only statistic tables and forc 95 Display only statistic tables and force stdio mode.
102 96
103 --full-symbols:: 97 --full-symbols::
104 Display full length of symbols. 98 Display full length of symbols.
105 99
106 --no-source:: 100 --no-source::
107 Do not display Source:Line column. 101 Do not display Source:Line column.
108 102
109 --show-all:: 103 --show-all::
110 Show all captured HITM lines, with no 104 Show all captured HITM lines, with no regard to HITM % 0.0005 limit.
111 105
112 -f:: 106 -f::
113 --force:: 107 --force::
114 Don't do ownership validation. 108 Don't do ownership validation.
115 109
116 -d:: 110 -d::
117 --display:: 111 --display::
118 Switch to HITM type (rmt, lcl) or peer !! 112 Switch to HITM type (rmt, lcl) to display and sort on. Total HITMs as default.
119 and sort on. Total HITMs (tot) as defa <<
120 as default. <<
121 <<
122 --stitch-lbr:: <<
123 Show callgraph with stitched LBRs, whi <<
124 callgraph. The perf.data file must hav <<
125 perf c2c record --call-graph lbr. <<
126 Disabled by default. In common cases w <<
127 it can recreate better call stacks tha <<
128 output. But this approach is not foolp <<
129 where it creates incorrect call stacks <<
130 The known limitations include exceptio <<
131 setjmp/longjmp will have calls/returns <<
132 <<
133 --double-cl:: <<
134 Group the detection of shared cachelin <<
135 granularity. Some architectures have a <<
136 feature, which causes cacheline sharin <<
137 size is doubled. <<
138 113
139 C2C RECORD 114 C2C RECORD
140 ---------- 115 ----------
141 The perf c2c record command setup options rela 116 The perf c2c record command setup options related to HITM cacheline analysis
142 and calls standard perf record command. 117 and calls standard perf record command.
143 118
144 Following perf record options are configured b 119 Following perf record options are configured by default:
145 (check perf record man page for details) 120 (check perf record man page for details)
146 121
147 -W,-d,--phys-data,--sample-cpu 122 -W,-d,--phys-data,--sample-cpu
148 123
149 Unless specified otherwise with '-e' option, f 124 Unless specified otherwise with '-e' option, following events are monitored by
150 default on Intel: !! 125 default on x86:
151 126
152 cpu/mem-loads,ldlat=30/P 127 cpu/mem-loads,ldlat=30/P
153 cpu/mem-stores/P 128 cpu/mem-stores/P
154 129
155 following on AMD: <<
156 <<
157 ibs_op// <<
158 <<
159 and following on PowerPC: 130 and following on PowerPC:
160 131
161 cpu/mem-loads/ 132 cpu/mem-loads/
162 cpu/mem-stores/ 133 cpu/mem-stores/
163 134
164 User can pass any 'perf record' option behind 135 User can pass any 'perf record' option behind '--' mark, like (to enable
165 callchains and system wide monitoring): 136 callchains and system wide monitoring):
166 137
167 $ perf c2c record -- -g -a 138 $ perf c2c record -- -g -a
168 139
169 Please check RECORD OPTIONS section for specif 140 Please check RECORD OPTIONS section for specific c2c record options.
170 141
171 C2C REPORT 142 C2C REPORT
172 ---------- 143 ----------
173 The perf c2c report command displays shared da 144 The perf c2c report command displays shared data analysis. It comes in two
174 display modes: stdio and tui (default). 145 display modes: stdio and tui (default).
175 146
176 The report command workflow is following: 147 The report command workflow is following:
177 - sort all the data based on the cacheline a 148 - sort all the data based on the cacheline address
178 - store access details for each cacheline 149 - store access details for each cacheline
179 - sort all cachelines based on user settings 150 - sort all cachelines based on user settings
180 - display data 151 - display data
181 152
182 In general perf report output consist of 2 bas 153 In general perf report output consist of 2 basic views:
183 1) most expensive cachelines list 154 1) most expensive cachelines list
184 2) offsets details for each cacheline 155 2) offsets details for each cacheline
185 156
186 For each cacheline in the 1) list we display f 157 For each cacheline in the 1) list we display following data:
187 (Both stdio and TUI modes follow the same fiel 158 (Both stdio and TUI modes follow the same fields output)
188 159
189 Index 160 Index
190 - zero based index to identify the cacheline 161 - zero based index to identify the cacheline
191 162
192 Cacheline 163 Cacheline
193 - cacheline address (hex number) 164 - cacheline address (hex number)
194 165
195 Rmt/Lcl Hitm (Display with HITM types) !! 166 Total records
196 - cacheline percentage of all Remote/Local H !! 167 - sum of all cachelines accesses
197 168
198 Peer Snoop (Display with peer type) !! 169 Rmt/Lcl Hitm
199 - cacheline percentage of all peer accesses !! 170 - cacheline percentage of all Remote/Local HITM accesses
200 171
201 LLC Load Hitm - Total, LclHitm, RmtHitm (For !! 172 LLC Load Hitm - Total, Lcl, Rmt
202 - count of Total/Local/Remote load HITMs 173 - count of Total/Local/Remote load HITMs
203 174
204 Load Peer - Total, Local, Remote (For displa !! 175 Store Reference - Total, L1Hit, L1Miss
205 - count of Total/Local/Remote load from peer !! 176 Total - all store accesses
206 !! 177 L1Hit - store accesses that hit L1
207 Total records !! 178 L1Hit - store accesses that missed L1
208 - sum of all cachelines accesses <<
209 179
210 Total loads !! 180 Load Dram
211 - sum of all load accesses !! 181 - count of local and remote DRAM accesses
212 182
213 Total stores !! 183 LLC Ld Miss
214 - sum of all store accesses !! 184 - count of all accesses that missed LLC
215 185
216 Store Reference - L1Hit, L1Miss, N/A !! 186 Total Loads
217 L1Hit - store accesses that hit L1 !! 187 - sum of all load accesses
218 L1Miss - store accesses that missed L1 <<
219 N/A - store accesses with memory level is <<
220 188
221 Core Load Hit - FB, L1, L2 189 Core Load Hit - FB, L1, L2
222 - count of load hits in FB (Fill Buffer), L1 190 - count of load hits in FB (Fill Buffer), L1 and L2 cache
223 191
224 LLC Load Hit - LlcHit, LclHitm !! 192 LLC Load Hit - Llc, Rmt
225 - count of LLC load accesses, includes LLC h !! 193 - count of LLC and Remote load hits
226 <<
227 RMT Load Hit - RmtHit, RmtHitm <<
228 - count of remote load accesses, includes re <<
229 on Arm neoverse cores, RmtHit is used to a <<
230 includes remote DRAM or any upward cache l <<
231 <<
232 Load Dram - Lcl, Rmt <<
233 - count of local and remote DRAM accesses <<
234 194
235 For each offset in the 2) list we display foll 195 For each offset in the 2) list we display following data:
236 196
237 HITM - Rmt, Lcl (Display with HITM types) !! 197 HITM - Rmt, Lcl
238 - % of Remote/Local HITM accesses for given 198 - % of Remote/Local HITM accesses for given offset within cacheline
239 199
240 Peer Snoop - Rmt, Lcl (Display with peer typ !! 200 Store Refs - L1 Hit, L1 Miss
241 - % of Remote/Local peer accesses for given !! 201 - % of store accesses that hit/missed L1 for given offset within cacheline
242 <<
243 Store Refs - L1 Hit, L1 Miss, N/A <<
244 - % of store accesses that hit L1, missed L1 <<
245 level for given offset within cacheline <<
246 202
247 Data address - Offset 203 Data address - Offset
248 - offset address 204 - offset address
249 205
250 Pid 206 Pid
251 - pid of the process responsible for the acc 207 - pid of the process responsible for the accesses
252 208
253 Tid 209 Tid
254 - tid of the process responsible for the acc 210 - tid of the process responsible for the accesses
255 211
256 Code address 212 Code address
257 - code address responsible for the accesses 213 - code address responsible for the accesses
258 214
259 cycles - rmt hitm, lcl hitm, load (Display w !! 215 cycles - rmt hitm, lcl hitm, load
260 - sum of cycles for given accesses - Remot 216 - sum of cycles for given accesses - Remote/Local HITM and generic load
261 217
262 cycles - rmt peer, lcl peer, load (Display w <<
263 - sum of cycles for given accesses - Remot <<
264 <<
265 cpu cnt 218 cpu cnt
266 - number of cpus that participated on the 219 - number of cpus that participated on the access
267 220
268 Symbol 221 Symbol
269 - code symbol related to the 'Code address 222 - code symbol related to the 'Code address' value
270 223
271 Shared Object 224 Shared Object
272 - shared object name related to the 'Code 225 - shared object name related to the 'Code address' value
273 226
274 Source:Line 227 Source:Line
275 - source information related to the 'Code 228 - source information related to the 'Code address' value
276 229
277 Node 230 Node
278 - nodes participating on the access (see N 231 - nodes participating on the access (see NODE INFO section)
279 232
280 NODE INFO 233 NODE INFO
281 --------- 234 ---------
282 The 'Node' field displays nodes that accesses 235 The 'Node' field displays nodes that accesses given cacheline
283 offset. Its output comes in 3 flavors: 236 offset. Its output comes in 3 flavors:
284 - node IDs separated by ',' 237 - node IDs separated by ','
285 - node IDs with stats for each ID, in follow 238 - node IDs with stats for each ID, in following format:
286 Node{cpus %hitms %stores} (Display with !! 239 Node{cpus %hitms %stores}
287 Node{cpus %peers %stores} (Display with <<
288 - node IDs with list of affected CPUs in fol 240 - node IDs with list of affected CPUs in following format:
289 Node{cpu list} 241 Node{cpu list}
290 242
291 User can switch between above flavors with -N 243 User can switch between above flavors with -N option or
292 use 'n' key to interactively switch in TUI mod 244 use 'n' key to interactively switch in TUI mode.
293 245
294 COALESCE 246 COALESCE
295 -------- 247 --------
296 User can specify how to sort offsets for cache 248 User can specify how to sort offsets for cacheline.
297 249
298 Following fields are available and governs the 250 Following fields are available and governs the final
299 output fields set for cacheline offsets output !! 251 output fields set for caheline offsets output:
300 252
301 tid - coalesced by process TIDs 253 tid - coalesced by process TIDs
302 pid - coalesced by process PIDs 254 pid - coalesced by process PIDs
303 iaddr - coalesced by code address, following 255 iaddr - coalesced by code address, following fields are displayed:
304 Code address, Code symbol, Shared 256 Code address, Code symbol, Shared Object, Source line
305 dso - coalesced by shared object 257 dso - coalesced by shared object
306 258
307 By default the coalescing is setup with 'pid,i 259 By default the coalescing is setup with 'pid,iaddr'.
308 260
309 STDIO OUTPUT 261 STDIO OUTPUT
310 ------------ 262 ------------
311 The stdio output displays data on standard out 263 The stdio output displays data on standard output.
312 264
313 Following tables are displayed: 265 Following tables are displayed:
314 Trace Event Information 266 Trace Event Information
315 - overall statistics of memory accesses 267 - overall statistics of memory accesses
316 268
317 Global Shared Cache Line Event Information 269 Global Shared Cache Line Event Information
318 - overall statistics on shared cachelines 270 - overall statistics on shared cachelines
319 271
320 Shared Data Cache Line Table 272 Shared Data Cache Line Table
321 - list of most expensive cachelines 273 - list of most expensive cachelines
322 274
323 Shared Cache Line Distribution Pareto 275 Shared Cache Line Distribution Pareto
324 - list of all accessed offsets for each cach 276 - list of all accessed offsets for each cacheline
325 277
326 TUI OUTPUT 278 TUI OUTPUT
327 ---------- 279 ----------
328 The TUI output provides interactive interface 280 The TUI output provides interactive interface to navigate
329 through cachelines list and to display offset 281 through cachelines list and to display offset details.
330 282
331 For details please refer to the help window by 283 For details please refer to the help window by pressing '?' key.
332 284
333 CREDITS 285 CREDITS
334 ------- 286 -------
335 Although Don Zickus, Dick Fowles and Joe Mario 287 Although Don Zickus, Dick Fowles and Joe Mario worked together
336 to get this implemented, we got lots of early 288 to get this implemented, we got lots of early help from Arnaldo
337 Carvalho de Melo, Stephane Eranian, Jiri Olsa 289 Carvalho de Melo, Stephane Eranian, Jiri Olsa and Andi Kleen.
338 290
339 C2C BLOG 291 C2C BLOG
340 -------- 292 --------
341 Check Joe's blog on c2c tool for detailed use 293 Check Joe's blog on c2c tool for detailed use case explanation:
342 https://joemario.github.io/blog/2016/09/01/c 294 https://joemario.github.io/blog/2016/09/01/c2c-blog/
343 295
344 SEE ALSO 296 SEE ALSO
345 -------- 297 --------
346 linkperf:perf-record[1], linkperf:perf-mem[1], !! 298 linkperf:perf-record[1], linkperf:perf-mem[1]
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