1 perf-c2c(1) 1 perf-c2c(1)
2 =========== 2 ===========
3 3
4 NAME 4 NAME
5 ---- 5 ----
6 perf-c2c - Shared Data C2C/HITM Analyzer. 6 perf-c2c - Shared Data C2C/HITM Analyzer.
7 7
8 SYNOPSIS 8 SYNOPSIS
9 -------- 9 --------
10 [verse] 10 [verse]
11 'perf c2c record' [<options>] <command> 11 'perf c2c record' [<options>] <command>
12 'perf c2c record' [<options>] \-- [<record com 12 'perf c2c record' [<options>] \-- [<record command options>] <command>
13 'perf c2c report' [<options>] 13 'perf c2c report' [<options>]
14 14
15 DESCRIPTION 15 DESCRIPTION
16 ----------- 16 -----------
17 C2C stands for Cache To Cache. 17 C2C stands for Cache To Cache.
18 18
19 The perf c2c tool provides means for Shared Da 19 The perf c2c tool provides means for Shared Data C2C/HITM analysis. It allows
20 you to track down the cacheline contentions. 20 you to track down the cacheline contentions.
21 21
22 On Intel, the tool is based on load latency an 22 On Intel, the tool is based on load latency and precise store facility events
23 provided by Intel CPUs. On PowerPC, the tool u 23 provided by Intel CPUs. On PowerPC, the tool uses random instruction sampling
24 with thresholding feature. On AMD, the tool us 24 with thresholding feature. On AMD, the tool uses IBS op pmu (due to hardware
25 limitations, perf c2c is not supported on Zen3 !! 25 limitations, perf c2c is not supported on Zen3 cpus).
26 sample load and store operations, therefore ha <<
27 required. See linkperf:perf-arm-spe[1] for a s <<
28 statistical nature of Arm SPE sampling, not ev <<
29 sampled. <<
30 26
31 These events provide: 27 These events provide:
32 - memory address of the access 28 - memory address of the access
33 - type of the access (load and store details 29 - type of the access (load and store details)
34 - latency (in cycles) of the load access 30 - latency (in cycles) of the load access
35 31
36 The c2c tool provide means to record this data 32 The c2c tool provide means to record this data and report back access details
37 for cachelines with highest contention - highe 33 for cachelines with highest contention - highest number of HITM accesses.
38 34
39 The basic workflow with this tool follows the 35 The basic workflow with this tool follows the standard record/report phase.
40 User uses the record command to record events 36 User uses the record command to record events data and report command to
41 display it. 37 display it.
42 38
43 39
44 RECORD OPTIONS 40 RECORD OPTIONS
45 -------------- 41 --------------
46 -e:: 42 -e::
47 --event=:: 43 --event=::
48 Select the PMU event. Use 'perf c2c re 44 Select the PMU event. Use 'perf c2c record -e list'
49 to list available events. 45 to list available events.
50 46
51 -v:: 47 -v::
52 --verbose:: 48 --verbose::
53 Be more verbose (show counter open err 49 Be more verbose (show counter open errors, etc).
54 50
55 -l:: 51 -l::
56 --ldlat:: 52 --ldlat::
57 Configure mem-loads latency. Supported 53 Configure mem-loads latency. Supported on Intel and Arm64 processors
58 only. Ignored on other archs. 54 only. Ignored on other archs.
59 55
60 -k:: 56 -k::
61 --all-kernel:: 57 --all-kernel::
62 Configure all used events to run in ke 58 Configure all used events to run in kernel space.
63 59
64 -u:: 60 -u::
65 --all-user:: 61 --all-user::
66 Configure all used events to run in us 62 Configure all used events to run in user space.
67 63
68 REPORT OPTIONS 64 REPORT OPTIONS
69 -------------- 65 --------------
70 -k:: 66 -k::
71 --vmlinux=<file>:: 67 --vmlinux=<file>::
72 vmlinux pathname 68 vmlinux pathname
73 69
74 -v:: 70 -v::
75 --verbose:: 71 --verbose::
76 Be more verbose (show counter open err 72 Be more verbose (show counter open errors, etc).
77 73
78 -i:: 74 -i::
79 --input:: 75 --input::
80 Specify the input file to process. 76 Specify the input file to process.
81 77
82 -N:: 78 -N::
83 --node-info:: 79 --node-info::
84 Show extra node info in report (see NO 80 Show extra node info in report (see NODE INFO section)
85 81
86 -c:: 82 -c::
87 --coalesce:: 83 --coalesce::
88 Specify sorting fields for single cach 84 Specify sorting fields for single cacheline display.
89 Following fields are available: tid,pi 85 Following fields are available: tid,pid,iaddr,dso
90 (see COALESCE) 86 (see COALESCE)
91 87
92 -g:: 88 -g::
93 --call-graph:: 89 --call-graph::
94 Setup callchains parameters. 90 Setup callchains parameters.
95 Please refer to perf-report man page f 91 Please refer to perf-report man page for details.
96 92
97 --stdio:: 93 --stdio::
98 Force the stdio output (see STDIO OUTP 94 Force the stdio output (see STDIO OUTPUT)
99 95
100 --stats:: 96 --stats::
101 Display only statistic tables and forc 97 Display only statistic tables and force stdio mode.
102 98
103 --full-symbols:: 99 --full-symbols::
104 Display full length of symbols. 100 Display full length of symbols.
105 101
106 --no-source:: 102 --no-source::
107 Do not display Source:Line column. 103 Do not display Source:Line column.
108 104
109 --show-all:: 105 --show-all::
110 Show all captured HITM lines, with no 106 Show all captured HITM lines, with no regard to HITM % 0.0005 limit.
111 107
112 -f:: 108 -f::
113 --force:: 109 --force::
114 Don't do ownership validation. 110 Don't do ownership validation.
115 111
116 -d:: 112 -d::
117 --display:: 113 --display::
118 Switch to HITM type (rmt, lcl) or peer 114 Switch to HITM type (rmt, lcl) or peer snooping type (peer) to display
119 and sort on. Total HITMs (tot) as defa 115 and sort on. Total HITMs (tot) as default, except Arm64 uses peer mode
120 as default. 116 as default.
121 117
122 --stitch-lbr:: 118 --stitch-lbr::
123 Show callgraph with stitched LBRs, whi 119 Show callgraph with stitched LBRs, which may have more complete
124 callgraph. The perf.data file must hav 120 callgraph. The perf.data file must have been obtained using
125 perf c2c record --call-graph lbr. 121 perf c2c record --call-graph lbr.
126 Disabled by default. In common cases w 122 Disabled by default. In common cases with call stack overflows,
127 it can recreate better call stacks tha 123 it can recreate better call stacks than the default lbr call stack
128 output. But this approach is not foolp !! 124 output. But this approach is not full proof. There can be cases
129 where it creates incorrect call stacks 125 where it creates incorrect call stacks from incorrect matches.
130 The known limitations include exceptio 126 The known limitations include exception handing such as
131 setjmp/longjmp will have calls/returns 127 setjmp/longjmp will have calls/returns not match.
132 128
133 --double-cl:: <<
134 Group the detection of shared cachelin <<
135 granularity. Some architectures have a <<
136 feature, which causes cacheline sharin <<
137 size is doubled. <<
138 <<
139 C2C RECORD 129 C2C RECORD
140 ---------- 130 ----------
141 The perf c2c record command setup options rela 131 The perf c2c record command setup options related to HITM cacheline analysis
142 and calls standard perf record command. 132 and calls standard perf record command.
143 133
144 Following perf record options are configured b 134 Following perf record options are configured by default:
145 (check perf record man page for details) 135 (check perf record man page for details)
146 136
147 -W,-d,--phys-data,--sample-cpu 137 -W,-d,--phys-data,--sample-cpu
148 138
149 Unless specified otherwise with '-e' option, f 139 Unless specified otherwise with '-e' option, following events are monitored by
150 default on Intel: 140 default on Intel:
151 141
152 cpu/mem-loads,ldlat=30/P 142 cpu/mem-loads,ldlat=30/P
153 cpu/mem-stores/P 143 cpu/mem-stores/P
154 144
155 following on AMD: 145 following on AMD:
156 146
157 ibs_op// 147 ibs_op//
158 148
159 and following on PowerPC: 149 and following on PowerPC:
160 150
161 cpu/mem-loads/ 151 cpu/mem-loads/
162 cpu/mem-stores/ 152 cpu/mem-stores/
163 153
164 User can pass any 'perf record' option behind 154 User can pass any 'perf record' option behind '--' mark, like (to enable
165 callchains and system wide monitoring): 155 callchains and system wide monitoring):
166 156
167 $ perf c2c record -- -g -a 157 $ perf c2c record -- -g -a
168 158
169 Please check RECORD OPTIONS section for specif 159 Please check RECORD OPTIONS section for specific c2c record options.
170 160
171 C2C REPORT 161 C2C REPORT
172 ---------- 162 ----------
173 The perf c2c report command displays shared da 163 The perf c2c report command displays shared data analysis. It comes in two
174 display modes: stdio and tui (default). 164 display modes: stdio and tui (default).
175 165
176 The report command workflow is following: 166 The report command workflow is following:
177 - sort all the data based on the cacheline a 167 - sort all the data based on the cacheline address
178 - store access details for each cacheline 168 - store access details for each cacheline
179 - sort all cachelines based on user settings 169 - sort all cachelines based on user settings
180 - display data 170 - display data
181 171
182 In general perf report output consist of 2 bas 172 In general perf report output consist of 2 basic views:
183 1) most expensive cachelines list 173 1) most expensive cachelines list
184 2) offsets details for each cacheline 174 2) offsets details for each cacheline
185 175
186 For each cacheline in the 1) list we display f 176 For each cacheline in the 1) list we display following data:
187 (Both stdio and TUI modes follow the same fiel 177 (Both stdio and TUI modes follow the same fields output)
188 178
189 Index 179 Index
190 - zero based index to identify the cacheline 180 - zero based index to identify the cacheline
191 181
192 Cacheline 182 Cacheline
193 - cacheline address (hex number) 183 - cacheline address (hex number)
194 184
195 Rmt/Lcl Hitm (Display with HITM types) 185 Rmt/Lcl Hitm (Display with HITM types)
196 - cacheline percentage of all Remote/Local H 186 - cacheline percentage of all Remote/Local HITM accesses
197 187
198 Peer Snoop (Display with peer type) 188 Peer Snoop (Display with peer type)
199 - cacheline percentage of all peer accesses 189 - cacheline percentage of all peer accesses
200 190
201 LLC Load Hitm - Total, LclHitm, RmtHitm (For 191 LLC Load Hitm - Total, LclHitm, RmtHitm (For display with HITM types)
202 - count of Total/Local/Remote load HITMs 192 - count of Total/Local/Remote load HITMs
203 193
204 Load Peer - Total, Local, Remote (For displa 194 Load Peer - Total, Local, Remote (For display with peer type)
205 - count of Total/Local/Remote load from peer 195 - count of Total/Local/Remote load from peer cache or DRAM
206 196
207 Total records 197 Total records
208 - sum of all cachelines accesses 198 - sum of all cachelines accesses
209 199
210 Total loads 200 Total loads
211 - sum of all load accesses 201 - sum of all load accesses
212 202
213 Total stores 203 Total stores
214 - sum of all store accesses 204 - sum of all store accesses
215 205
216 Store Reference - L1Hit, L1Miss, N/A 206 Store Reference - L1Hit, L1Miss, N/A
217 L1Hit - store accesses that hit L1 207 L1Hit - store accesses that hit L1
218 L1Miss - store accesses that missed L1 208 L1Miss - store accesses that missed L1
219 N/A - store accesses with memory level is 209 N/A - store accesses with memory level is not available
220 210
221 Core Load Hit - FB, L1, L2 211 Core Load Hit - FB, L1, L2
222 - count of load hits in FB (Fill Buffer), L1 212 - count of load hits in FB (Fill Buffer), L1 and L2 cache
223 213
224 LLC Load Hit - LlcHit, LclHitm 214 LLC Load Hit - LlcHit, LclHitm
225 - count of LLC load accesses, includes LLC h 215 - count of LLC load accesses, includes LLC hits and LLC HITMs
226 216
227 RMT Load Hit - RmtHit, RmtHitm 217 RMT Load Hit - RmtHit, RmtHitm
228 - count of remote load accesses, includes re 218 - count of remote load accesses, includes remote hits and remote HITMs;
229 on Arm neoverse cores, RmtHit is used to a 219 on Arm neoverse cores, RmtHit is used to account remote accesses,
230 includes remote DRAM or any upward cache l 220 includes remote DRAM or any upward cache level in remote node
231 221
232 Load Dram - Lcl, Rmt 222 Load Dram - Lcl, Rmt
233 - count of local and remote DRAM accesses 223 - count of local and remote DRAM accesses
234 224
235 For each offset in the 2) list we display foll 225 For each offset in the 2) list we display following data:
236 226
237 HITM - Rmt, Lcl (Display with HITM types) 227 HITM - Rmt, Lcl (Display with HITM types)
238 - % of Remote/Local HITM accesses for given 228 - % of Remote/Local HITM accesses for given offset within cacheline
239 229
240 Peer Snoop - Rmt, Lcl (Display with peer typ 230 Peer Snoop - Rmt, Lcl (Display with peer type)
241 - % of Remote/Local peer accesses for given 231 - % of Remote/Local peer accesses for given offset within cacheline
242 232
243 Store Refs - L1 Hit, L1 Miss, N/A 233 Store Refs - L1 Hit, L1 Miss, N/A
244 - % of store accesses that hit L1, missed L1 234 - % of store accesses that hit L1, missed L1 and N/A (no available) memory
245 level for given offset within cacheline 235 level for given offset within cacheline
246 236
247 Data address - Offset 237 Data address - Offset
248 - offset address 238 - offset address
249 239
250 Pid 240 Pid
251 - pid of the process responsible for the acc 241 - pid of the process responsible for the accesses
252 242
253 Tid 243 Tid
254 - tid of the process responsible for the acc 244 - tid of the process responsible for the accesses
255 245
256 Code address 246 Code address
257 - code address responsible for the accesses 247 - code address responsible for the accesses
258 248
259 cycles - rmt hitm, lcl hitm, load (Display w 249 cycles - rmt hitm, lcl hitm, load (Display with HITM types)
260 - sum of cycles for given accesses - Remot 250 - sum of cycles for given accesses - Remote/Local HITM and generic load
261 251
262 cycles - rmt peer, lcl peer, load (Display w 252 cycles - rmt peer, lcl peer, load (Display with peer type)
263 - sum of cycles for given accesses - Remot 253 - sum of cycles for given accesses - Remote/Local peer load and generic load
264 254
265 cpu cnt 255 cpu cnt
266 - number of cpus that participated on the 256 - number of cpus that participated on the access
267 257
268 Symbol 258 Symbol
269 - code symbol related to the 'Code address 259 - code symbol related to the 'Code address' value
270 260
271 Shared Object 261 Shared Object
272 - shared object name related to the 'Code 262 - shared object name related to the 'Code address' value
273 263
274 Source:Line 264 Source:Line
275 - source information related to the 'Code 265 - source information related to the 'Code address' value
276 266
277 Node 267 Node
278 - nodes participating on the access (see N 268 - nodes participating on the access (see NODE INFO section)
279 269
280 NODE INFO 270 NODE INFO
281 --------- 271 ---------
282 The 'Node' field displays nodes that accesses 272 The 'Node' field displays nodes that accesses given cacheline
283 offset. Its output comes in 3 flavors: 273 offset. Its output comes in 3 flavors:
284 - node IDs separated by ',' 274 - node IDs separated by ','
285 - node IDs with stats for each ID, in follow 275 - node IDs with stats for each ID, in following format:
286 Node{cpus %hitms %stores} (Display with 276 Node{cpus %hitms %stores} (Display with HITM types)
287 Node{cpus %peers %stores} (Display with 277 Node{cpus %peers %stores} (Display with peer type)
288 - node IDs with list of affected CPUs in fol 278 - node IDs with list of affected CPUs in following format:
289 Node{cpu list} 279 Node{cpu list}
290 280
291 User can switch between above flavors with -N 281 User can switch between above flavors with -N option or
292 use 'n' key to interactively switch in TUI mod 282 use 'n' key to interactively switch in TUI mode.
293 283
294 COALESCE 284 COALESCE
295 -------- 285 --------
296 User can specify how to sort offsets for cache 286 User can specify how to sort offsets for cacheline.
297 287
298 Following fields are available and governs the 288 Following fields are available and governs the final
299 output fields set for cacheline offsets output 289 output fields set for cacheline offsets output:
300 290
301 tid - coalesced by process TIDs 291 tid - coalesced by process TIDs
302 pid - coalesced by process PIDs 292 pid - coalesced by process PIDs
303 iaddr - coalesced by code address, following 293 iaddr - coalesced by code address, following fields are displayed:
304 Code address, Code symbol, Shared 294 Code address, Code symbol, Shared Object, Source line
305 dso - coalesced by shared object 295 dso - coalesced by shared object
306 296
307 By default the coalescing is setup with 'pid,i 297 By default the coalescing is setup with 'pid,iaddr'.
308 298
309 STDIO OUTPUT 299 STDIO OUTPUT
310 ------------ 300 ------------
311 The stdio output displays data on standard out 301 The stdio output displays data on standard output.
312 302
313 Following tables are displayed: 303 Following tables are displayed:
314 Trace Event Information 304 Trace Event Information
315 - overall statistics of memory accesses 305 - overall statistics of memory accesses
316 306
317 Global Shared Cache Line Event Information 307 Global Shared Cache Line Event Information
318 - overall statistics on shared cachelines 308 - overall statistics on shared cachelines
319 309
320 Shared Data Cache Line Table 310 Shared Data Cache Line Table
321 - list of most expensive cachelines 311 - list of most expensive cachelines
322 312
323 Shared Cache Line Distribution Pareto 313 Shared Cache Line Distribution Pareto
324 - list of all accessed offsets for each cach 314 - list of all accessed offsets for each cacheline
325 315
326 TUI OUTPUT 316 TUI OUTPUT
327 ---------- 317 ----------
328 The TUI output provides interactive interface 318 The TUI output provides interactive interface to navigate
329 through cachelines list and to display offset 319 through cachelines list and to display offset details.
330 320
331 For details please refer to the help window by 321 For details please refer to the help window by pressing '?' key.
332 322
333 CREDITS 323 CREDITS
334 ------- 324 -------
335 Although Don Zickus, Dick Fowles and Joe Mario 325 Although Don Zickus, Dick Fowles and Joe Mario worked together
336 to get this implemented, we got lots of early 326 to get this implemented, we got lots of early help from Arnaldo
337 Carvalho de Melo, Stephane Eranian, Jiri Olsa 327 Carvalho de Melo, Stephane Eranian, Jiri Olsa and Andi Kleen.
338 328
339 C2C BLOG 329 C2C BLOG
340 -------- 330 --------
341 Check Joe's blog on c2c tool for detailed use 331 Check Joe's blog on c2c tool for detailed use case explanation:
342 https://joemario.github.io/blog/2016/09/01/c 332 https://joemario.github.io/blog/2016/09/01/c2c-blog/
343 333
344 SEE ALSO 334 SEE ALSO
345 -------- 335 --------
346 linkperf:perf-record[1], linkperf:perf-mem[1], !! 336 linkperf:perf-record[1], linkperf:perf-mem[1]
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