1 1
2 Performance Counters for Linux 2 Performance Counters for Linux
3 ------------------------------ 3 ------------------------------
4 4
5 Performance counters are special hardware regi 5 Performance counters are special hardware registers available on most modern
6 CPUs. These registers count the number of cert 6 CPUs. These registers count the number of certain types of hw events: such
7 as instructions executed, cachemisses suffered 7 as instructions executed, cachemisses suffered, or branches mis-predicted -
8 without slowing down the kernel or application 8 without slowing down the kernel or applications. These registers can also
9 trigger interrupts when a threshold number of 9 trigger interrupts when a threshold number of events have passed - and can
10 thus be used to profile the code that runs on 10 thus be used to profile the code that runs on that CPU.
11 11
12 The Linux Performance Counter subsystem provid 12 The Linux Performance Counter subsystem provides an abstraction of these
13 hardware capabilities. It provides per task an 13 hardware capabilities. It provides per task and per CPU counters, counter
14 groups, and it provides event capabilities on 14 groups, and it provides event capabilities on top of those. It
15 provides "virtual" 64-bit counters, regardless 15 provides "virtual" 64-bit counters, regardless of the width of the
16 underlying hardware counters. 16 underlying hardware counters.
17 17
18 Performance counters are accessed via special 18 Performance counters are accessed via special file descriptors.
19 There's one file descriptor per virtual counte 19 There's one file descriptor per virtual counter used.
20 20
21 The special file descriptor is opened via the 21 The special file descriptor is opened via the sys_perf_event_open()
22 system call: 22 system call:
23 23
24 int sys_perf_event_open(struct perf_event_a 24 int sys_perf_event_open(struct perf_event_attr *hw_event_uptr,
25 pid_t pid, int cp 25 pid_t pid, int cpu, int group_fd,
26 unsigned long fla 26 unsigned long flags);
27 27
28 The syscall returns the new fd. The fd can be 28 The syscall returns the new fd. The fd can be used via the normal
29 VFS system calls: read() can be used to read t 29 VFS system calls: read() can be used to read the counter, fcntl()
30 can be used to set the blocking mode, etc. 30 can be used to set the blocking mode, etc.
31 31
32 Multiple counters can be kept open at a time, 32 Multiple counters can be kept open at a time, and the counters
33 can be poll()ed. 33 can be poll()ed.
34 34
35 When creating a new counter fd, 'perf_event_at 35 When creating a new counter fd, 'perf_event_attr' is:
36 36
37 struct perf_event_attr { 37 struct perf_event_attr {
38 /* 38 /*
39 * The MSB of the config word signifie 39 * The MSB of the config word signifies if the rest contains cpu
40 * specific (raw) counter configuratio 40 * specific (raw) counter configuration data, if unset, the next
41 * 7 bits are an event type and the re 41 * 7 bits are an event type and the rest of the bits are the event
42 * identifier. 42 * identifier.
43 */ 43 */
44 __u64 config; 44 __u64 config;
45 45
46 __u64 irq_period; 46 __u64 irq_period;
47 __u32 record_type; 47 __u32 record_type;
48 __u32 read_format; 48 __u32 read_format;
49 49
50 __u64 disabled 50 __u64 disabled : 1, /* off by default */
51 inherit 51 inherit : 1, /* children inherit it */
52 pinned 52 pinned : 1, /* must always be on PMU */
53 exclusive 53 exclusive : 1, /* only group on PMU */
54 exclude_user 54 exclude_user : 1, /* don't count user */
55 exclude_kernel 55 exclude_kernel : 1, /* ditto kernel */
56 exclude_hv 56 exclude_hv : 1, /* ditto hypervisor */
57 exclude_idle 57 exclude_idle : 1, /* don't count when idle */
58 mmap 58 mmap : 1, /* include mmap data */
59 munmap 59 munmap : 1, /* include munmap data */
60 comm 60 comm : 1, /* include comm data */
61 61
62 __reserved_1 62 __reserved_1 : 52;
63 63
64 __u32 extra_config_l 64 __u32 extra_config_len;
65 __u32 wakeup_events; 65 __u32 wakeup_events; /* wakeup every n events */
66 66
67 __u64 __reserved_2; 67 __u64 __reserved_2;
68 __u64 __reserved_3; 68 __u64 __reserved_3;
69 }; 69 };
70 70
71 The 'config' field specifies what the counter 71 The 'config' field specifies what the counter should count. It
72 is divided into 3 bit-fields: 72 is divided into 3 bit-fields:
73 73
74 raw_type: 1 bit (most significant bit) 74 raw_type: 1 bit (most significant bit) 0x8000_0000_0000_0000
75 type: 7 bits (next most significant) 75 type: 7 bits (next most significant) 0x7f00_0000_0000_0000
76 event_id: 56 bits (least significant) 76 event_id: 56 bits (least significant) 0x00ff_ffff_ffff_ffff
77 77
78 If 'raw_type' is 1, then the counter will coun 78 If 'raw_type' is 1, then the counter will count a hardware event
79 specified by the remaining 63 bits of event_co 79 specified by the remaining 63 bits of event_config. The encoding is
80 machine-specific. 80 machine-specific.
81 81
82 If 'raw_type' is 0, then the 'type' field says 82 If 'raw_type' is 0, then the 'type' field says what kind of counter
83 this is, with the following encoding: 83 this is, with the following encoding:
84 84
85 enum perf_type_id { 85 enum perf_type_id {
86 PERF_TYPE_HARDWARE = 0, 86 PERF_TYPE_HARDWARE = 0,
87 PERF_TYPE_SOFTWARE = 1, 87 PERF_TYPE_SOFTWARE = 1,
88 PERF_TYPE_TRACEPOINT = 2, 88 PERF_TYPE_TRACEPOINT = 2,
89 }; 89 };
90 90
91 A counter of PERF_TYPE_HARDWARE will count the 91 A counter of PERF_TYPE_HARDWARE will count the hardware event
92 specified by 'event_id': 92 specified by 'event_id':
93 93
94 /* 94 /*
95 * Generalized performance counter event types 95 * Generalized performance counter event types, used by the hw_event.event_id
96 * parameter of the sys_perf_event_open() sysc 96 * parameter of the sys_perf_event_open() syscall:
97 */ 97 */
98 enum perf_hw_id { 98 enum perf_hw_id {
99 /* 99 /*
100 * Common hardware events, generalized 100 * Common hardware events, generalized by the kernel:
101 */ 101 */
102 PERF_COUNT_HW_CPU_CYCLES 102 PERF_COUNT_HW_CPU_CYCLES = 0,
103 PERF_COUNT_HW_INSTRUCTIONS 103 PERF_COUNT_HW_INSTRUCTIONS = 1,
104 PERF_COUNT_HW_CACHE_REFERENCES 104 PERF_COUNT_HW_CACHE_REFERENCES = 2,
105 PERF_COUNT_HW_CACHE_MISSES 105 PERF_COUNT_HW_CACHE_MISSES = 3,
106 PERF_COUNT_HW_BRANCH_INSTRUCTIONS 106 PERF_COUNT_HW_BRANCH_INSTRUCTIONS = 4,
107 PERF_COUNT_HW_BRANCH_MISSES 107 PERF_COUNT_HW_BRANCH_MISSES = 5,
108 PERF_COUNT_HW_BUS_CYCLES 108 PERF_COUNT_HW_BUS_CYCLES = 6,
109 PERF_COUNT_HW_STALLED_CYCLES_FRONTEND <<
110 PERF_COUNT_HW_STALLED_CYCLES_BACKEND <<
111 PERF_COUNT_HW_REF_CPU_CYCLES <<
112 }; 109 };
113 110
114 These are standardized types of events that wo 111 These are standardized types of events that work relatively uniformly
115 on all CPUs that implement Performance Counter 112 on all CPUs that implement Performance Counters support under Linux,
116 although there may be variations (e.g., differ 113 although there may be variations (e.g., different CPUs might count
117 cache references and misses at different level 114 cache references and misses at different levels of the cache hierarchy).
118 If a CPU is not able to count the selected eve 115 If a CPU is not able to count the selected event, then the system call
119 will return -EINVAL. 116 will return -EINVAL.
120 117
121 More hw_event_types are supported as well, but 118 More hw_event_types are supported as well, but they are CPU-specific
122 and accessed as raw events. For example, to c 119 and accessed as raw events. For example, to count "External bus
123 cycles while bus lock signal asserted" events 120 cycles while bus lock signal asserted" events on Intel Core CPUs, pass
124 in a 0x4064 event_id value and set hw_event.ra 121 in a 0x4064 event_id value and set hw_event.raw_type to 1.
125 122
126 A counter of type PERF_TYPE_SOFTWARE will coun 123 A counter of type PERF_TYPE_SOFTWARE will count one of the available
127 software events, selected by 'event_id': 124 software events, selected by 'event_id':
128 125
129 /* 126 /*
130 * Special "software" counters provided by the 127 * Special "software" counters provided by the kernel, even if the hardware
131 * does not support performance counters. Thes 128 * does not support performance counters. These counters measure various
132 * physical and sw events of the kernel (and a 129 * physical and sw events of the kernel (and allow the profiling of them as
133 * well): 130 * well):
134 */ 131 */
135 enum perf_sw_ids { 132 enum perf_sw_ids {
136 PERF_COUNT_SW_CPU_CLOCK = 0, 133 PERF_COUNT_SW_CPU_CLOCK = 0,
137 PERF_COUNT_SW_TASK_CLOCK = 1, 134 PERF_COUNT_SW_TASK_CLOCK = 1,
138 PERF_COUNT_SW_PAGE_FAULTS = 2, 135 PERF_COUNT_SW_PAGE_FAULTS = 2,
139 PERF_COUNT_SW_CONTEXT_SWITCHES = 3, 136 PERF_COUNT_SW_CONTEXT_SWITCHES = 3,
140 PERF_COUNT_SW_CPU_MIGRATIONS = 4, 137 PERF_COUNT_SW_CPU_MIGRATIONS = 4,
141 PERF_COUNT_SW_PAGE_FAULTS_MIN = 5, 138 PERF_COUNT_SW_PAGE_FAULTS_MIN = 5,
142 PERF_COUNT_SW_PAGE_FAULTS_MAJ = 6, 139 PERF_COUNT_SW_PAGE_FAULTS_MAJ = 6,
143 PERF_COUNT_SW_ALIGNMENT_FAULTS = 7, 140 PERF_COUNT_SW_ALIGNMENT_FAULTS = 7,
144 PERF_COUNT_SW_EMULATION_FAULTS = 8, 141 PERF_COUNT_SW_EMULATION_FAULTS = 8,
145 }; 142 };
146 143
147 Counters of the type PERF_TYPE_TRACEPOINT are 144 Counters of the type PERF_TYPE_TRACEPOINT are available when the ftrace event
148 tracer is available, and event_id values can b 145 tracer is available, and event_id values can be obtained from
149 /debug/tracing/events/*/*/id 146 /debug/tracing/events/*/*/id
150 147
151 148
152 Counters come in two flavours: counting counte 149 Counters come in two flavours: counting counters and sampling
153 counters. A "counting" counter is one that is 150 counters. A "counting" counter is one that is used for counting the
154 number of events that occur, and is characteri 151 number of events that occur, and is characterised by having
155 irq_period = 0. 152 irq_period = 0.
156 153
157 154
158 A read() on a counter returns the current valu 155 A read() on a counter returns the current value of the counter and possible
159 additional values as specified by 'read_format 156 additional values as specified by 'read_format', each value is a u64 (8 bytes)
160 in size. 157 in size.
161 158
162 /* 159 /*
163 * Bits that can be set in hw_event.read_forma 160 * Bits that can be set in hw_event.read_format to request that
164 * reads on the counter should return the indi 161 * reads on the counter should return the indicated quantities,
165 * in increasing order of bit value, after the 162 * in increasing order of bit value, after the counter value.
166 */ 163 */
167 enum perf_event_read_format { 164 enum perf_event_read_format {
168 PERF_FORMAT_TOTAL_TIME_ENABLED = 1, 165 PERF_FORMAT_TOTAL_TIME_ENABLED = 1,
169 PERF_FORMAT_TOTAL_TIME_RUNNING = 2, 166 PERF_FORMAT_TOTAL_TIME_RUNNING = 2,
170 }; 167 };
171 168
172 Using these additional values one can establis 169 Using these additional values one can establish the overcommit ratio for a
173 particular counter allowing one to take the ro 170 particular counter allowing one to take the round-robin scheduling effect
174 into account. 171 into account.
175 172
176 173
177 A "sampling" counter is one that is set up to 174 A "sampling" counter is one that is set up to generate an interrupt
178 every N events, where N is given by 'irq_perio 175 every N events, where N is given by 'irq_period'. A sampling counter
179 has irq_period > 0. The record_type controls w 176 has irq_period > 0. The record_type controls what data is recorded on each
180 interrupt: 177 interrupt:
181 178
182 /* 179 /*
183 * Bits that can be set in hw_event.record_typ 180 * Bits that can be set in hw_event.record_type to request information
184 * in the overflow packets. 181 * in the overflow packets.
185 */ 182 */
186 enum perf_event_record_format { 183 enum perf_event_record_format {
187 PERF_RECORD_IP = 1U << 0, 184 PERF_RECORD_IP = 1U << 0,
188 PERF_RECORD_TID = 1U << 1, 185 PERF_RECORD_TID = 1U << 1,
189 PERF_RECORD_TIME = 1U << 2, 186 PERF_RECORD_TIME = 1U << 2,
190 PERF_RECORD_ADDR = 1U << 3, 187 PERF_RECORD_ADDR = 1U << 3,
191 PERF_RECORD_GROUP = 1U << 4, 188 PERF_RECORD_GROUP = 1U << 4,
192 PERF_RECORD_CALLCHAIN = 1U << 5, 189 PERF_RECORD_CALLCHAIN = 1U << 5,
193 }; 190 };
194 191
195 Such (and other) events will be recorded in a 192 Such (and other) events will be recorded in a ring-buffer, which is
196 available to user-space using mmap() (see belo 193 available to user-space using mmap() (see below).
197 194
198 The 'disabled' bit specifies whether the count 195 The 'disabled' bit specifies whether the counter starts out disabled
199 or enabled. If it is initially disabled, it c 196 or enabled. If it is initially disabled, it can be enabled by ioctl
200 or prctl (see below). 197 or prctl (see below).
201 198
202 The 'inherit' bit, if set, specifies that this 199 The 'inherit' bit, if set, specifies that this counter should count
203 events on descendant tasks as well as the task 200 events on descendant tasks as well as the task specified. This only
204 applies to new descendents, not to any existin 201 applies to new descendents, not to any existing descendents at the
205 time the counter is created (nor to any new de 202 time the counter is created (nor to any new descendents of existing
206 descendents). 203 descendents).
207 204
208 The 'pinned' bit, if set, specifies that the c 205 The 'pinned' bit, if set, specifies that the counter should always be
209 on the CPU if at all possible. It only applie 206 on the CPU if at all possible. It only applies to hardware counters
210 and only to group leaders. If a pinned counte 207 and only to group leaders. If a pinned counter cannot be put onto the
211 CPU (e.g. because there are not enough hardwar 208 CPU (e.g. because there are not enough hardware counters or because of
212 a conflict with some other event), then the co 209 a conflict with some other event), then the counter goes into an
213 'error' state, where reads return end-of-file 210 'error' state, where reads return end-of-file (i.e. read() returns 0)
214 until the counter is subsequently enabled or d 211 until the counter is subsequently enabled or disabled.
215 212
216 The 'exclusive' bit, if set, specifies that wh 213 The 'exclusive' bit, if set, specifies that when this counter's group
217 is on the CPU, it should be the only group usi 214 is on the CPU, it should be the only group using the CPU's counters.
218 In future, this will allow sophisticated monit 215 In future, this will allow sophisticated monitoring programs to supply
219 extra configuration information via 'extra_con 216 extra configuration information via 'extra_config_len' to exploit
220 advanced features of the CPU's Performance Mon 217 advanced features of the CPU's Performance Monitor Unit (PMU) that are
221 not otherwise accessible and that might disrup 218 not otherwise accessible and that might disrupt other hardware
222 counters. 219 counters.
223 220
224 The 'exclude_user', 'exclude_kernel' and 'excl 221 The 'exclude_user', 'exclude_kernel' and 'exclude_hv' bits provide a
225 way to request that counting of events be rest 222 way to request that counting of events be restricted to times when the
226 CPU is in user, kernel and/or hypervisor mode. 223 CPU is in user, kernel and/or hypervisor mode.
227 224
228 Furthermore the 'exclude_host' and 'exclude_gu 225 Furthermore the 'exclude_host' and 'exclude_guest' bits provide a way
229 to request counting of events restricted to gu 226 to request counting of events restricted to guest and host contexts when
230 using Linux as the hypervisor. 227 using Linux as the hypervisor.
231 228
232 The 'mmap' and 'munmap' bits allow recording o 229 The 'mmap' and 'munmap' bits allow recording of PROT_EXEC mmap/munmap
233 operations, these can be used to relate usersp 230 operations, these can be used to relate userspace IP addresses to actual
234 code, even after the mapping (or even the whol 231 code, even after the mapping (or even the whole process) is gone,
235 these events are recorded in the ring-buffer ( 232 these events are recorded in the ring-buffer (see below).
236 233
237 The 'comm' bit allows tracking of process comm 234 The 'comm' bit allows tracking of process comm data on process creation.
238 This too is recorded in the ring-buffer (see b 235 This too is recorded in the ring-buffer (see below).
239 236
240 The 'pid' parameter to the sys_perf_event_open 237 The 'pid' parameter to the sys_perf_event_open() system call allows the
241 counter to be specific to a task: 238 counter to be specific to a task:
242 239
243 pid == 0: if the pid parameter is zero, the c 240 pid == 0: if the pid parameter is zero, the counter is attached to the
244 current task. 241 current task.
245 242
246 pid > 0: the counter is attached to a specifi 243 pid > 0: the counter is attached to a specific task (if the current task
247 has sufficient privilege to do so) 244 has sufficient privilege to do so)
248 245
249 pid < 0: all tasks are counted (per cpu count 246 pid < 0: all tasks are counted (per cpu counters)
250 247
251 The 'cpu' parameter allows a counter to be mad 248 The 'cpu' parameter allows a counter to be made specific to a CPU:
252 249
253 cpu >= 0: the counter is restricted to a spec 250 cpu >= 0: the counter is restricted to a specific CPU
254 cpu == -1: the counter counts on all CPUs 251 cpu == -1: the counter counts on all CPUs
255 252
256 (Note: the combination of 'pid == -1' and 'cpu 253 (Note: the combination of 'pid == -1' and 'cpu == -1' is not valid.)
257 254
258 A 'pid > 0' and 'cpu == -1' counter is a per t 255 A 'pid > 0' and 'cpu == -1' counter is a per task counter that counts
259 events of that task and 'follows' that task to 256 events of that task and 'follows' that task to whatever CPU the task
260 gets schedule to. Per task counters can be cre 257 gets schedule to. Per task counters can be created by any user, for
261 their own tasks. 258 their own tasks.
262 259
263 A 'pid == -1' and 'cpu == x' counter is a per 260 A 'pid == -1' and 'cpu == x' counter is a per CPU counter that counts
264 all events on CPU-x. Per CPU counters need CAP 261 all events on CPU-x. Per CPU counters need CAP_PERFMON or CAP_SYS_ADMIN
265 privilege. 262 privilege.
266 263
267 The 'flags' parameter is currently unused and 264 The 'flags' parameter is currently unused and must be zero.
268 265
269 The 'group_fd' parameter allows counter "group 266 The 'group_fd' parameter allows counter "groups" to be set up. A
270 counter group has one counter which is the gro 267 counter group has one counter which is the group "leader". The leader
271 is created first, with group_fd = -1 in the sy 268 is created first, with group_fd = -1 in the sys_perf_event_open call
272 that creates it. The rest of the group member 269 that creates it. The rest of the group members are created
273 subsequently, with group_fd giving the fd of t 270 subsequently, with group_fd giving the fd of the group leader.
274 (A single counter on its own is created with g 271 (A single counter on its own is created with group_fd = -1 and is
275 considered to be a group with only 1 member.) 272 considered to be a group with only 1 member.)
276 273
277 A counter group is scheduled onto the CPU as a 274 A counter group is scheduled onto the CPU as a unit, that is, it will
278 only be put onto the CPU if all of the counter 275 only be put onto the CPU if all of the counters in the group can be
279 put onto the CPU. This means that the values 276 put onto the CPU. This means that the values of the member counters
280 can be meaningfully compared, added, divided ( 277 can be meaningfully compared, added, divided (to get ratios), etc.,
281 with each other, since they have counted event 278 with each other, since they have counted events for the same set of
282 executed instructions. 279 executed instructions.
283 280
284 281
285 Like stated, asynchronous events, like counter 282 Like stated, asynchronous events, like counter overflow or PROT_EXEC mmap
286 tracking are logged into a ring-buffer. This r 283 tracking are logged into a ring-buffer. This ring-buffer is created and
287 accessed through mmap(). 284 accessed through mmap().
288 285
289 The mmap size should be 1+2^n pages, where the 286 The mmap size should be 1+2^n pages, where the first page is a meta-data page
290 (struct perf_event_mmap_page) that contains va 287 (struct perf_event_mmap_page) that contains various bits of information such
291 as where the ring-buffer head is. 288 as where the ring-buffer head is.
292 289
293 /* 290 /*
294 * Structure of the page that can be mapped vi 291 * Structure of the page that can be mapped via mmap
295 */ 292 */
296 struct perf_event_mmap_page { 293 struct perf_event_mmap_page {
297 __u32 version; /* ver 294 __u32 version; /* version number of this structure */
298 __u32 compat_version; /* low 295 __u32 compat_version; /* lowest version this is compat with */
299 296
300 /* 297 /*
301 * Bits needed to read the hw counters 298 * Bits needed to read the hw counters in user-space.
302 * 299 *
303 * u32 seq; 300 * u32 seq;
304 * s64 count; 301 * s64 count;
305 * 302 *
306 * do { 303 * do {
307 * seq = pc->lock; 304 * seq = pc->lock;
308 * 305 *
309 * barrier() 306 * barrier()
310 * if (pc->index) { 307 * if (pc->index) {
311 * count = pmc_read(pc->index - 308 * count = pmc_read(pc->index - 1);
312 * count += pc->offset; 309 * count += pc->offset;
313 * } else 310 * } else
314 * goto regular_read; 311 * goto regular_read;
315 * 312 *
316 * barrier(); 313 * barrier();
317 * } while (pc->lock != seq); 314 * } while (pc->lock != seq);
318 * 315 *
319 * NOTE: for obvious reason this only 316 * NOTE: for obvious reason this only works on self-monitoring
320 * processes. 317 * processes.
321 */ 318 */
322 __u32 lock; /* seq 319 __u32 lock; /* seqlock for synchronization */
323 __u32 index; /* har 320 __u32 index; /* hardware counter identifier */
324 __s64 offset; /* add 321 __s64 offset; /* add to hardware counter value */
325 322
326 /* 323 /*
327 * Control data for the mmap() data bu 324 * Control data for the mmap() data buffer.
328 * 325 *
329 * User-space reading this value shoul 326 * User-space reading this value should issue an rmb(), on SMP capable
330 * platforms, after reading this value 327 * platforms, after reading this value -- see perf_event_wakeup().
331 */ 328 */
332 __u32 data_head; /* hea 329 __u32 data_head; /* head in the data section */
333 }; 330 };
334 331
335 NOTE: the hw-counter userspace bits are arch s 332 NOTE: the hw-counter userspace bits are arch specific and are currently only
336 implemented on powerpc. 333 implemented on powerpc.
337 334
338 The following 2^n pages are the ring-buffer wh 335 The following 2^n pages are the ring-buffer which contains events of the form:
339 336
340 #define PERF_RECORD_MISC_KERNEL (1 << 337 #define PERF_RECORD_MISC_KERNEL (1 << 0)
341 #define PERF_RECORD_MISC_USER (1 << 338 #define PERF_RECORD_MISC_USER (1 << 1)
342 #define PERF_RECORD_MISC_OVERFLOW (1 << 339 #define PERF_RECORD_MISC_OVERFLOW (1 << 2)
343 340
344 struct perf_event_header { 341 struct perf_event_header {
345 __u32 type; 342 __u32 type;
346 __u16 misc; 343 __u16 misc;
347 __u16 size; 344 __u16 size;
348 }; 345 };
349 346
350 enum perf_event_type { 347 enum perf_event_type {
351 348
352 /* 349 /*
353 * The MMAP events record the PROT_EXE 350 * The MMAP events record the PROT_EXEC mappings so that we can
354 * correlate userspace IPs to code. Th 351 * correlate userspace IPs to code. They have the following structure:
355 * 352 *
356 * struct { 353 * struct {
357 * struct perf_event_header 354 * struct perf_event_header header;
358 * 355 *
359 * u32 356 * u32 pid, tid;
360 * u64 357 * u64 addr;
361 * u64 358 * u64 len;
362 * u64 359 * u64 pgoff;
363 * char 360 * char filename[];
364 * }; 361 * };
365 */ 362 */
366 PERF_RECORD_MMAP = 1, 363 PERF_RECORD_MMAP = 1,
367 PERF_RECORD_MUNMAP = 2, 364 PERF_RECORD_MUNMAP = 2,
368 365
369 /* 366 /*
370 * struct { 367 * struct {
371 * struct perf_event_header 368 * struct perf_event_header header;
372 * 369 *
373 * u32 370 * u32 pid, tid;
374 * char 371 * char comm[];
375 * }; 372 * };
376 */ 373 */
377 PERF_RECORD_COMM = 3, 374 PERF_RECORD_COMM = 3,
378 375
379 /* 376 /*
380 * When header.misc & PERF_RECORD_MISC 377 * When header.misc & PERF_RECORD_MISC_OVERFLOW the event_type field
381 * will be PERF_RECORD_* 378 * will be PERF_RECORD_*
382 * 379 *
383 * struct { 380 * struct {
384 * struct perf_event_header 381 * struct perf_event_header header;
385 * 382 *
386 * { u64 ip; 383 * { u64 ip; } && PERF_RECORD_IP
387 * { u32 pid, t 384 * { u32 pid, tid; } && PERF_RECORD_TID
388 * { u64 time; 385 * { u64 time; } && PERF_RECORD_TIME
389 * { u64 addr; 386 * { u64 addr; } && PERF_RECORD_ADDR
390 * 387 *
391 * { u64 nr; 388 * { u64 nr;
392 * { u64 event, val; } cnt[nr 389 * { u64 event, val; } cnt[nr]; } && PERF_RECORD_GROUP
393 * 390 *
394 * { u16 nr, 391 * { u16 nr,
395 * hv, 392 * hv,
396 * kernel 393 * kernel,
397 * user; 394 * user;
398 * u64 ips[nr 395 * u64 ips[nr]; } && PERF_RECORD_CALLCHAIN
399 * }; 396 * };
400 */ 397 */
401 }; 398 };
402 399
403 NOTE: PERF_RECORD_CALLCHAIN is arch specific a 400 NOTE: PERF_RECORD_CALLCHAIN is arch specific and currently only implemented
404 on x86. 401 on x86.
405 402
406 Notification of new events is possible through 403 Notification of new events is possible through poll()/select()/epoll() and
407 fcntl() managing signals. 404 fcntl() managing signals.
408 405
409 Normally a notification is generated for every 406 Normally a notification is generated for every page filled, however one can
410 additionally set perf_event_attr.wakeup_events 407 additionally set perf_event_attr.wakeup_events to generate one every
411 so many counter overflow events. 408 so many counter overflow events.
412 409
413 Future work will include a splice() interface 410 Future work will include a splice() interface to the ring-buffer.
414 411
415 412
416 Counters can be enabled and disabled in two wa 413 Counters can be enabled and disabled in two ways: via ioctl and via
417 prctl. When a counter is disabled, it doesn't 414 prctl. When a counter is disabled, it doesn't count or generate
418 events but does continue to exist and maintain 415 events but does continue to exist and maintain its count value.
419 416
420 An individual counter can be enabled with 417 An individual counter can be enabled with
421 418
422 ioctl(fd, PERF_EVENT_IOC_ENABLE, 0); 419 ioctl(fd, PERF_EVENT_IOC_ENABLE, 0);
423 420
424 or disabled with 421 or disabled with
425 422
426 ioctl(fd, PERF_EVENT_IOC_DISABLE, 0); 423 ioctl(fd, PERF_EVENT_IOC_DISABLE, 0);
427 424
428 For a counter group, pass PERF_IOC_FLAG_GROUP 425 For a counter group, pass PERF_IOC_FLAG_GROUP as the third argument.
429 Enabling or disabling the leader of a group en 426 Enabling or disabling the leader of a group enables or disables the
430 whole group; that is, while the group leader i 427 whole group; that is, while the group leader is disabled, none of the
431 counters in the group will count. Enabling or 428 counters in the group will count. Enabling or disabling a member of a
432 group other than the leader only affects that 429 group other than the leader only affects that counter - disabling an
433 non-leader stops that counter from counting bu 430 non-leader stops that counter from counting but doesn't affect any
434 other counter. 431 other counter.
435 432
436 Additionally, non-inherited overflow counters 433 Additionally, non-inherited overflow counters can use
437 434
438 ioctl(fd, PERF_EVENT_IOC_REFRESH, nr); 435 ioctl(fd, PERF_EVENT_IOC_REFRESH, nr);
439 436
440 to enable a counter for 'nr' events, after whi 437 to enable a counter for 'nr' events, after which it gets disabled again.
441 438
442 A process can enable or disable all the counte 439 A process can enable or disable all the counter groups that are
443 attached to it, using prctl: 440 attached to it, using prctl:
444 441
445 prctl(PR_TASK_PERF_EVENTS_ENABLE); 442 prctl(PR_TASK_PERF_EVENTS_ENABLE);
446 443
447 prctl(PR_TASK_PERF_EVENTS_DISABLE); 444 prctl(PR_TASK_PERF_EVENTS_DISABLE);
448 445
449 This applies to all counters on the current pr 446 This applies to all counters on the current process, whether created
450 by this process or by another, and doesn't aff 447 by this process or by another, and doesn't affect any counters that
451 this process has created on other processes. 448 this process has created on other processes. It only enables or
452 disables the group leaders, not any other memb 449 disables the group leaders, not any other members in the groups.
453 450
454 451
455 Arch requirements 452 Arch requirements
456 ----------------- 453 -----------------
457 454
458 If your architecture does not have hardware pe 455 If your architecture does not have hardware performance metrics, you can
459 still use the generic software counters based 456 still use the generic software counters based on hrtimers for sampling.
460 457
461 So to start with, in order to add HAVE_PERF_EV 458 So to start with, in order to add HAVE_PERF_EVENTS to your Kconfig, you
462 will need at least this: 459 will need at least this:
463 - asm/perf_event.h - a basic stub will 460 - asm/perf_event.h - a basic stub will suffice at first
464 - support for atomic64 types (and asso 461 - support for atomic64 types (and associated helper functions)
465 462
466 If your architecture does have hardware capabi 463 If your architecture does have hardware capabilities, you can override the
467 weak stub hw_perf_event_init() to register har 464 weak stub hw_perf_event_init() to register hardware counters.
468 465
469 Architectures that have d-cache aliassing issu 466 Architectures that have d-cache aliassing issues, such as Sparc and ARM,
470 should select PERF_USE_VMALLOC in order to avo 467 should select PERF_USE_VMALLOC in order to avoid these for perf mmap().
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