1 [config] 1 [config] 2 command = stat 2 command = stat 3 args = -dd kill >/dev/null 2>&1 3 args = -dd kill >/dev/null 2>&1 4 ret = 1 4 ret = 1 5 5 6 6 7 # PERF_TYPE_SOFTWARE / PERF_COUNT_SW_TASK_CLOC 7 # PERF_TYPE_SOFTWARE / PERF_COUNT_SW_TASK_CLOCK 8 [event1:base-stat] 8 [event1:base-stat] 9 fd=1 9 fd=1 10 type=1 10 type=1 11 config=1 11 config=1 12 12 13 # PERF_TYPE_SOFTWARE / PERF_COUNT_SW_CONTEXT_S 13 # PERF_TYPE_SOFTWARE / PERF_COUNT_SW_CONTEXT_SWITCHES 14 [event2:base-stat] 14 [event2:base-stat] 15 fd=2 15 fd=2 16 type=1 16 type=1 17 config=3 17 config=3 18 18 19 # PERF_TYPE_SOFTWARE / PERF_COUNT_SW_CPU_MIGRA 19 # PERF_TYPE_SOFTWARE / PERF_COUNT_SW_CPU_MIGRATIONS 20 [event3:base-stat] 20 [event3:base-stat] 21 fd=3 21 fd=3 22 type=1 22 type=1 23 config=4 23 config=4 24 24 25 # PERF_TYPE_SOFTWARE / PERF_COUNT_SW_PAGE_FAUL 25 # PERF_TYPE_SOFTWARE / PERF_COUNT_SW_PAGE_FAULTS 26 [event4:base-stat] 26 [event4:base-stat] 27 fd=4 27 fd=4 28 type=1 28 type=1 29 config=2 29 config=2 30 30 31 # PERF_TYPE_HARDWARE / PERF_COUNT_HW_CPU_CYCLE 31 # PERF_TYPE_HARDWARE / PERF_COUNT_HW_CPU_CYCLES 32 [event5:base-stat] 32 [event5:base-stat] 33 fd=5 33 fd=5 34 type=0 34 type=0 35 config=0 35 config=0 36 optional=1 << 37 36 38 # PERF_TYPE_HARDWARE / PERF_COUNT_HW_STALLED_C 37 # PERF_TYPE_HARDWARE / PERF_COUNT_HW_STALLED_CYCLES_FRONTEND 39 [event6:base-stat] 38 [event6:base-stat] 40 fd=6 39 fd=6 41 type=0 40 type=0 42 config=7 41 config=7 43 optional=1 << 44 42 45 # PERF_TYPE_HARDWARE / PERF_COUNT_HW_STALLED_C 43 # PERF_TYPE_HARDWARE / PERF_COUNT_HW_STALLED_CYCLES_BACKEND 46 [event7:base-stat] 44 [event7:base-stat] 47 fd=7 45 fd=7 48 type=0 46 type=0 49 config=8 47 config=8 50 optional=1 << 51 48 52 # PERF_TYPE_HARDWARE / PERF_COUNT_HW_INSTRUCTI 49 # PERF_TYPE_HARDWARE / PERF_COUNT_HW_INSTRUCTIONS 53 [event8:base-stat] 50 [event8:base-stat] 54 fd=8 51 fd=8 55 type=0 52 type=0 56 config=1 53 config=1 57 optional=1 << 58 54 59 # PERF_TYPE_HARDWARE / PERF_COUNT_HW_BRANCH_IN 55 # PERF_TYPE_HARDWARE / PERF_COUNT_HW_BRANCH_INSTRUCTIONS 60 [event9:base-stat] 56 [event9:base-stat] 61 fd=9 57 fd=9 62 type=0 58 type=0 63 config=4 59 config=4 64 optional=1 << 65 60 66 # PERF_TYPE_HARDWARE / PERF_COUNT_HW_BRANCH_MI 61 # PERF_TYPE_HARDWARE / PERF_COUNT_HW_BRANCH_MISSES 67 [event10:base-stat] 62 [event10:base-stat] 68 fd=10 63 fd=10 69 type=0 64 type=0 70 config=5 65 config=5 71 optional=1 << 72 << 73 # PERF_TYPE_RAW / slots (0x400) << 74 [event11:base-stat] << 75 fd=11 << 76 group_fd=-1 << 77 type=4 << 78 config=1024 << 79 read_format=15 << 80 optional=1 << 81 << 82 # PERF_TYPE_RAW / topdown-retiring (0x8000) << 83 [event12:base-stat] << 84 fd=12 << 85 group_fd=11 << 86 type=4 << 87 config=32768 << 88 disabled=0 << 89 enable_on_exec=0 << 90 read_format=15 << 91 optional=1 << 92 << 93 # PERF_TYPE_RAW / topdown-fe-bound (0x8200) << 94 [event13:base-stat] << 95 fd=13 << 96 group_fd=11 << 97 type=4 << 98 config=33280 << 99 disabled=0 << 100 enable_on_exec=0 << 101 read_format=15 << 102 optional=1 << 103 << 104 # PERF_TYPE_RAW / topdown-be-bound (0x8300) << 105 [event14:base-stat] << 106 fd=14 << 107 group_fd=11 << 108 type=4 << 109 config=33536 << 110 disabled=0 << 111 enable_on_exec=0 << 112 read_format=15 << 113 optional=1 << 114 << 115 # PERF_TYPE_RAW / topdown-bad-spec (0x8100) << 116 [event15:base-stat] << 117 fd=15 << 118 group_fd=11 << 119 type=4 << 120 config=33024 << 121 disabled=0 << 122 enable_on_exec=0 << 123 read_format=15 << 124 optional=1 << 125 << 126 # PERF_TYPE_RAW / INT_MISC.UOP_DROPPING << 127 [event16:base-stat] << 128 fd=16 << 129 type=4 << 130 config=4109 << 131 optional=1 << 132 << 133 # PERF_TYPE_RAW / cpu/INT_MISC.RECOVERY_CYCLES << 134 [event17:base-stat] << 135 fd=17 << 136 type=4 << 137 config=17039629 << 138 optional=1 << 139 << 140 # PERF_TYPE_RAW / CPU_CLK_UNHALTED.THREAD << 141 [event18:base-stat] << 142 fd=18 << 143 type=4 << 144 config=60 << 145 optional=1 << 146 << 147 # PERF_TYPE_RAW / INT_MISC.RECOVERY_CYCLES_ANY << 148 [event19:base-stat] << 149 fd=19 << 150 type=4 << 151 config=2097421 << 152 optional=1 << 153 << 154 # PERF_TYPE_RAW / CPU_CLK_UNHALTED.REF_XCLK << 155 [event20:base-stat] << 156 fd=20 << 157 type=4 << 158 config=316 << 159 optional=1 << 160 << 161 # PERF_TYPE_RAW / IDQ_UOPS_NOT_DELIVERED.CORE << 162 [event21:base-stat] << 163 fd=21 << 164 type=4 << 165 config=412 << 166 optional=1 << 167 << 168 # PERF_TYPE_RAW / CPU_CLK_UNHALTED.ONE_THREAD_ << 169 [event22:base-stat] << 170 fd=22 << 171 type=4 << 172 config=572 << 173 optional=1 << 174 << 175 # PERF_TYPE_RAW / UOPS_RETIRED.RETIRE_SLOTS << 176 [event23:base-stat] << 177 fd=23 << 178 type=4 << 179 config=706 << 180 optional=1 << 181 << 182 # PERF_TYPE_RAW / UOPS_ISSUED.ANY << 183 [event24:base-stat] << 184 fd=24 << 185 type=4 << 186 config=270 << 187 optional=1 << 188 66 189 # PERF_TYPE_HW_CACHE / 67 # PERF_TYPE_HW_CACHE / 190 # PERF_COUNT_HW_CACHE_L1D << 68 # PERF_COUNT_HW_CACHE_L1D << 0 | 191 # (PERF_COUNT_HW_CACHE_OP_READ << 69 # (PERF_COUNT_HW_CACHE_OP_READ << 8) | 192 # (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 1 70 # (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16) 193 [event25:base-stat] !! 71 [event11:base-stat] 194 fd=25 !! 72 fd=11 195 type=3 73 type=3 196 config=0 74 config=0 197 optional=1 << 198 75 199 # PERF_TYPE_HW_CACHE / 76 # PERF_TYPE_HW_CACHE / 200 # PERF_COUNT_HW_CACHE_L1D << 77 # PERF_COUNT_HW_CACHE_L1D << 0 | 201 # (PERF_COUNT_HW_CACHE_OP_READ << 78 # (PERF_COUNT_HW_CACHE_OP_READ << 8) | 202 # (PERF_COUNT_HW_CACHE_RESULT_MISS << 1 79 # (PERF_COUNT_HW_CACHE_RESULT_MISS << 16) 203 [event26:base-stat] !! 80 [event12:base-stat] 204 fd=26 !! 81 fd=12 205 type=3 82 type=3 206 config=65536 83 config=65536 207 optional=1 << 208 84 209 # PERF_TYPE_HW_CACHE / 85 # PERF_TYPE_HW_CACHE / 210 # PERF_COUNT_HW_CACHE_LL << 86 # PERF_COUNT_HW_CACHE_LL << 0 | 211 # (PERF_COUNT_HW_CACHE_OP_READ << 87 # (PERF_COUNT_HW_CACHE_OP_READ << 8) | 212 # (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 1 88 # (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16) 213 [event27:base-stat] !! 89 [event13:base-stat] 214 fd=27 !! 90 fd=13 215 type=3 91 type=3 216 config=2 92 config=2 217 optional=1 << 218 93 219 # PERF_TYPE_HW_CACHE, 94 # PERF_TYPE_HW_CACHE, 220 # PERF_COUNT_HW_CACHE_LL << 95 # PERF_COUNT_HW_CACHE_LL << 0 | 221 # (PERF_COUNT_HW_CACHE_OP_READ << 96 # (PERF_COUNT_HW_CACHE_OP_READ << 8) | 222 # (PERF_COUNT_HW_CACHE_RESULT_MISS << 1 97 # (PERF_COUNT_HW_CACHE_RESULT_MISS << 16) 223 [event28:base-stat] !! 98 [event14:base-stat] 224 fd=28 !! 99 fd=14 225 type=3 100 type=3 226 config=65538 101 config=65538 227 optional=1 << 228 102 229 # PERF_TYPE_HW_CACHE, 103 # PERF_TYPE_HW_CACHE, 230 # PERF_COUNT_HW_CACHE_L1I << 104 # PERF_COUNT_HW_CACHE_L1I << 0 | 231 # (PERF_COUNT_HW_CACHE_OP_READ << 105 # (PERF_COUNT_HW_CACHE_OP_READ << 8) | 232 # (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 1 106 # (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16) 233 [event29:base-stat] !! 107 [event15:base-stat] 234 fd=29 !! 108 fd=15 235 type=3 109 type=3 236 config=1 110 config=1 237 optional=1 << 238 111 239 # PERF_TYPE_HW_CACHE, 112 # PERF_TYPE_HW_CACHE, 240 # PERF_COUNT_HW_CACHE_L1I << 113 # PERF_COUNT_HW_CACHE_L1I << 0 | 241 # (PERF_COUNT_HW_CACHE_OP_READ << 114 # (PERF_COUNT_HW_CACHE_OP_READ << 8) | 242 # (PERF_COUNT_HW_CACHE_RESULT_MISS << 1 115 # (PERF_COUNT_HW_CACHE_RESULT_MISS << 16) 243 [event30:base-stat] !! 116 [event16:base-stat] 244 fd=30 !! 117 fd=16 245 type=3 118 type=3 246 config=65537 119 config=65537 247 optional=1 << 248 120 249 # PERF_TYPE_HW_CACHE, 121 # PERF_TYPE_HW_CACHE, 250 # PERF_COUNT_HW_CACHE_DTLB << 122 # PERF_COUNT_HW_CACHE_DTLB << 0 | 251 # (PERF_COUNT_HW_CACHE_OP_READ << 123 # (PERF_COUNT_HW_CACHE_OP_READ << 8) | 252 # (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 1 124 # (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16) 253 [event31:base-stat] !! 125 [event17:base-stat] 254 fd=31 !! 126 fd=17 255 type=3 127 type=3 256 config=3 128 config=3 257 optional=1 << 258 129 259 # PERF_TYPE_HW_CACHE, 130 # PERF_TYPE_HW_CACHE, 260 # PERF_COUNT_HW_CACHE_DTLB << 131 # PERF_COUNT_HW_CACHE_DTLB << 0 | 261 # (PERF_COUNT_HW_CACHE_OP_READ << 132 # (PERF_COUNT_HW_CACHE_OP_READ << 8) | 262 # (PERF_COUNT_HW_CACHE_RESULT_MISS << 1 133 # (PERF_COUNT_HW_CACHE_RESULT_MISS << 16) 263 [event32:base-stat] !! 134 [event18:base-stat] 264 fd=32 !! 135 fd=18 265 type=3 136 type=3 266 config=65539 137 config=65539 267 optional=1 << 268 138 269 # PERF_TYPE_HW_CACHE, 139 # PERF_TYPE_HW_CACHE, 270 # PERF_COUNT_HW_CACHE_ITLB << 140 # PERF_COUNT_HW_CACHE_ITLB << 0 | 271 # (PERF_COUNT_HW_CACHE_OP_READ << 141 # (PERF_COUNT_HW_CACHE_OP_READ << 8) | 272 # (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 1 142 # (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16) 273 [event33:base-stat] !! 143 [event19:base-stat] 274 fd=33 !! 144 fd=19 275 type=3 145 type=3 276 config=4 146 config=4 277 optional=1 << 278 147 279 # PERF_TYPE_HW_CACHE, 148 # PERF_TYPE_HW_CACHE, 280 # PERF_COUNT_HW_CACHE_ITLB << 149 # PERF_COUNT_HW_CACHE_ITLB << 0 | 281 # (PERF_COUNT_HW_CACHE_OP_READ << 150 # (PERF_COUNT_HW_CACHE_OP_READ << 8) | 282 # (PERF_COUNT_HW_CACHE_RESULT_MISS << 1 151 # (PERF_COUNT_HW_CACHE_RESULT_MISS << 16) 283 [event34:base-stat] !! 152 [event20:base-stat] 284 fd=34 !! 153 fd=20 285 type=3 154 type=3 286 config=65540 155 config=65540 287 optional=1 <<
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.