1 /* SPDX-License-Identifier: GPL-2.0 */ 1
2 /*
3 * Copyright(C) 2015 Linaro Limited. All right
4 * Author: Mathieu Poirier <mathieu.poirier@li
5 */
6
7 #ifndef INCLUDE__UTIL_PERF_CS_ETM_H__
8 #define INCLUDE__UTIL_PERF_CS_ETM_H__
9
10 #include "debug.h"
11 #include "util/event.h"
12 #include <linux/bits.h>
13
14 struct perf_session;
15 struct perf_pmu;
16
17 /*
18 * Versioning header in case things need to ch
19 * decoding of old snapshot is still possible.
20 */
21 enum {
22 /* Starting with 0x0 */
23 CS_HEADER_VERSION,
24 /* PMU->type (32 bit), total # of CPUs
25 CS_PMU_TYPE_CPUS,
26 CS_ETM_SNAPSHOT,
27 CS_HEADER_VERSION_MAX,
28 };
29
30 /*
31 * Update the version for new format.
32 *
33 * Version 1: format adds a param count to the
34 * This allows easy adding of new metadata par
35 * Requires that new params always added after
36 * Also allows client reader to handle file ve
37 * checking the number of params in the file v
38 *
39 * Version 2: Drivers will use PERF_RECORD_AUX
40 * CoreSight Trace ID. ...TRACEIDR metadata wi
41 * but with addition flags.
42 */
43 #define CS_HEADER_CURRENT_VERSION 2
44
45 /* Beginning of header common to both ETMv3 an
46 enum {
47 CS_ETM_MAGIC,
48 CS_ETM_CPU,
49 /* Number of trace config params in fo
50 CS_ETM_NR_TRC_PARAMS,
51 CS_ETM_COMMON_BLK_MAX_V1,
52 };
53
54 /* ETMv3/PTM metadata */
55 enum {
56 /* Dynamic, configurable parameters */
57 CS_ETM_ETMCR = CS_ETM_COMMON_BLK_MAX_V
58 CS_ETM_ETMTRACEIDR,
59 /* RO, taken from sysFS */
60 CS_ETM_ETMCCER,
61 CS_ETM_ETMIDR,
62 CS_ETM_PRIV_MAX,
63 };
64
65 /* define fixed version 0 length - allow new f
66 #define CS_ETM_NR_TRC_PARAMS_V0 (CS_ETM_ETMIDR
67
68 /* ETMv4 metadata */
69 enum {
70 /* Dynamic, configurable parameters */
71 CS_ETMV4_TRCCONFIGR = CS_ETM_COMMON_BL
72 CS_ETMV4_TRCTRACEIDR,
73 /* RO, taken from sysFS */
74 CS_ETMV4_TRCIDR0,
75 CS_ETMV4_TRCIDR1,
76 CS_ETMV4_TRCIDR2,
77 CS_ETMV4_TRCIDR8,
78 CS_ETMV4_TRCAUTHSTATUS,
79 CS_ETMV4_TS_SOURCE,
80 CS_ETMV4_PRIV_MAX,
81 };
82
83 /* define fixed version 0 length - allow new f
84 #define CS_ETMV4_NR_TRC_PARAMS_V0 (CS_ETMV4_TR
85
86 /*
87 * ETE metadata is ETMv4 plus TRCDEVARCH regis
88 * added in header V1
89 */
90 enum {
91 /* Dynamic, configurable parameters */
92 CS_ETE_TRCCONFIGR = CS_ETM_COMMON_BLK_
93 CS_ETE_TRCTRACEIDR,
94 /* RO, taken from sysFS */
95 CS_ETE_TRCIDR0,
96 CS_ETE_TRCIDR1,
97 CS_ETE_TRCIDR2,
98 CS_ETE_TRCIDR8,
99 CS_ETE_TRCAUTHSTATUS,
100 CS_ETE_TRCDEVARCH,
101 CS_ETE_TS_SOURCE,
102 CS_ETE_PRIV_MAX
103 };
104
105 /*
106 * Check for valid CoreSight trace ID. If an i
107 * then IDs are present in the hardware ID pac
108 */
109 #define CS_IS_VALID_TRACE_ID(id) ((id > 0) &&
110
111 /*
112 * ETMv3 exception encoding number:
113 * See Embedded Trace Macrocell specification
114 * table 7-12 Encoding of Exception[3:0] for n
115 */
116 enum {
117 CS_ETMV3_EXC_NONE = 0,
118 CS_ETMV3_EXC_DEBUG_HALT = 1,
119 CS_ETMV3_EXC_SMC = 2,
120 CS_ETMV3_EXC_HYP = 3,
121 CS_ETMV3_EXC_ASYNC_DATA_ABORT = 4,
122 CS_ETMV3_EXC_JAZELLE_THUMBEE = 5,
123 CS_ETMV3_EXC_PE_RESET = 8,
124 CS_ETMV3_EXC_UNDEFINED_INSTR = 9,
125 CS_ETMV3_EXC_SVC = 10,
126 CS_ETMV3_EXC_PREFETCH_ABORT = 11,
127 CS_ETMV3_EXC_DATA_FAULT = 12,
128 CS_ETMV3_EXC_GENERIC = 13,
129 CS_ETMV3_EXC_IRQ = 14,
130 CS_ETMV3_EXC_FIQ = 15,
131 };
132
133 /*
134 * ETMv4 exception encoding number:
135 * See ARM Embedded Trace Macrocell Architectu
136 * table 6-12 Possible values for the TYPE fie
137 * trace packet, for ARMv7-A/R and ARMv8-A/R P
138 */
139 enum {
140 CS_ETMV4_EXC_RESET = 0,
141 CS_ETMV4_EXC_DEBUG_HALT = 1,
142 CS_ETMV4_EXC_CALL = 2,
143 CS_ETMV4_EXC_TRAP = 3,
144 CS_ETMV4_EXC_SYSTEM_ERROR = 4,
145 CS_ETMV4_EXC_INST_DEBUG = 6,
146 CS_ETMV4_EXC_DATA_DEBUG = 7,
147 CS_ETMV4_EXC_ALIGNMENT = 10,
148 CS_ETMV4_EXC_INST_FAULT = 11,
149 CS_ETMV4_EXC_DATA_FAULT = 12,
150 CS_ETMV4_EXC_IRQ = 14,
151 CS_ETMV4_EXC_FIQ = 15,
152 CS_ETMV4_EXC_END = 31,
153 };
154
155 enum cs_etm_sample_type {
156 CS_ETM_EMPTY,
157 CS_ETM_RANGE,
158 CS_ETM_DISCONTINUITY,
159 CS_ETM_EXCEPTION,
160 CS_ETM_EXCEPTION_RET,
161 };
162
163 enum cs_etm_isa {
164 CS_ETM_ISA_UNKNOWN,
165 CS_ETM_ISA_A64,
166 CS_ETM_ISA_A32,
167 CS_ETM_ISA_T32,
168 };
169
170 struct cs_etm_queue;
171
172 struct cs_etm_packet {
173 enum cs_etm_sample_type sample_type;
174 enum cs_etm_isa isa;
175 u64 start_addr;
176 u64 end_addr;
177 u32 instr_count;
178 u32 last_instr_type;
179 u32 last_instr_subtype;
180 u32 flags;
181 u32 exception_number;
182 bool last_instr_cond;
183 bool last_instr_taken_branch;
184 u8 last_instr_size;
185 u8 trace_chan_id;
186 int cpu;
187 };
188
189 #define CS_ETM_PACKET_MAX_BUFFER 1024
190
191 /*
192 * When working with per-thread scenarios the
193 * be scheduled on any CPU and as such, more t
194 * associated with the same process. Since a
195 * as per the CoreSight architecture, use that
196 * identify the queue where all packets (with
197 * aggregated.
198 */
199 #define CS_ETM_PER_THREAD_TRACEID 0
200
201 struct cs_etm_packet_queue {
202 u32 packet_count;
203 u32 head;
204 u32 tail;
205 u32 instr_count;
206 u64 cs_timestamp; /* Timestamp from tr
207 u64 next_cs_timestamp;
208 struct cs_etm_packet packet_buffer[CS_
209 };
210
211 #define KiB(x) ((x) * 1024)
212 #define MiB(x) ((x) * 1024 * 1024)
213
214 #define CS_ETM_INVAL_ADDR 0xdeadbeefdeadbeefUL
215
216 #define BMVAL(val, lsb, msb) ((val & GENMAS
217
218 #define CS_ETM_HEADER_SIZE (CS_HEADER_VERSION_
219
220 #define __perf_cs_etmv3_magic 0x30303030303030
221 #define __perf_cs_etmv4_magic 0x40404040404040
222 #define __perf_cs_ete_magic 0x50505050505050
223 #define CS_ETMV3_PRIV_SIZE (CS_ETM_PRIV_MAX *
224 #define CS_ETMV4_PRIV_SIZE (CS_ETMV4_PRIV_MAX
225 #define CS_ETE_PRIV_SIZE (CS_ETE_PRIV_MAX * si
226
227 #define INFO_HEADER_SIZE (sizeof(((struct perf
228 sizeof(((struct perf
229
230 /* CoreSight trace ID is currently the bottom
231 #define CORESIGHT_TRACE_ID_VAL_MASK GENMAS
232
233 int cs_etm__process_auxtrace_info(union perf_e
234 struct perf_
235 void cs_etm_get_default_config(const struct pe
236
237 enum cs_etm_pid_fmt {
238 CS_ETM_PIDFMT_NONE,
239 CS_ETM_PIDFMT_CTXTID,
240 CS_ETM_PIDFMT_CTXTID2
241 };
242
243 #ifdef HAVE_CSTRACE_SUPPORT
244 #include <opencsd/ocsd_if_types.h>
245 int cs_etm__get_cpu(struct cs_etm_queue *etmq,
246 enum cs_etm_pid_fmt cs_etm__get_pid_fmt(struct
247 int cs_etm__etmq_set_tid_el(struct cs_etm_queu
248 u8 trace_chan_id,
249 bool cs_etm__etmq_is_timeless(struct cs_etm_qu
250 void cs_etm__etmq_set_traceid_queue_timestamp(
251
252 struct cs_etm_packet_queue
253 *cs_etm__etmq_get_packet_queue(struct cs_etm_q
254 int cs_etm__process_auxtrace_info_full(union p
255 struct
256 u64 cs_etm__convert_sample_time(struct cs_etm_
257 #else
258 static inline int
259 cs_etm__process_auxtrace_info_full(union perf_
260 struct perf
261 {
262 pr_err("\nCS ETM Trace: OpenCSD is not
263 return -1;
264 }
265 #endif
266
267 #endif
268
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