1 /* SPDX-License-Identifier: GPL-2.0 */ 1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* 2 /*
3 * Copyright(C) 2015 Linaro Limited. All right 3 * Copyright(C) 2015 Linaro Limited. All rights reserved.
4 * Author: Mathieu Poirier <mathieu.poirier@li 4 * Author: Mathieu Poirier <mathieu.poirier@linaro.org>
5 */ 5 */
6 6
7 #ifndef INCLUDE__UTIL_PERF_CS_ETM_H__ 7 #ifndef INCLUDE__UTIL_PERF_CS_ETM_H__
8 #define INCLUDE__UTIL_PERF_CS_ETM_H__ 8 #define INCLUDE__UTIL_PERF_CS_ETM_H__
9 9
10 #include "debug.h" <<
11 #include "util/event.h" 10 #include "util/event.h"
12 #include <linux/bits.h> 11 #include <linux/bits.h>
13 12
14 struct perf_session; 13 struct perf_session;
15 struct perf_pmu; <<
16 14
17 /* !! 15 /* Versionning header in case things need tro change in the future. That way
18 * Versioning header in case things need to ch <<
19 * decoding of old snapshot is still possible. 16 * decoding of old snapshot is still possible.
20 */ 17 */
21 enum { 18 enum {
22 /* Starting with 0x0 */ 19 /* Starting with 0x0 */
23 CS_HEADER_VERSION, !! 20 CS_HEADER_VERSION_0,
24 /* PMU->type (32 bit), total # of CPUs 21 /* PMU->type (32 bit), total # of CPUs (32 bit) */
25 CS_PMU_TYPE_CPUS, 22 CS_PMU_TYPE_CPUS,
26 CS_ETM_SNAPSHOT, 23 CS_ETM_SNAPSHOT,
27 CS_HEADER_VERSION_MAX, !! 24 CS_HEADER_VERSION_0_MAX,
28 }; 25 };
29 26
30 /* <<
31 * Update the version for new format. <<
32 * <<
33 * Version 1: format adds a param count to the <<
34 * This allows easy adding of new metadata par <<
35 * Requires that new params always added after <<
36 * Also allows client reader to handle file ve <<
37 * checking the number of params in the file v <<
38 * <<
39 * Version 2: Drivers will use PERF_RECORD_AUX <<
40 * CoreSight Trace ID. ...TRACEIDR metadata wi <<
41 * but with addition flags. <<
42 */ <<
43 #define CS_HEADER_CURRENT_VERSION 2 <<
44 <<
45 /* Beginning of header common to both ETMv3 an 27 /* Beginning of header common to both ETMv3 and V4 */
46 enum { 28 enum {
47 CS_ETM_MAGIC, 29 CS_ETM_MAGIC,
48 CS_ETM_CPU, 30 CS_ETM_CPU,
49 /* Number of trace config params in fo <<
50 CS_ETM_NR_TRC_PARAMS, <<
51 CS_ETM_COMMON_BLK_MAX_V1, <<
52 }; 31 };
53 32
54 /* ETMv3/PTM metadata */ 33 /* ETMv3/PTM metadata */
55 enum { 34 enum {
56 /* Dynamic, configurable parameters */ 35 /* Dynamic, configurable parameters */
57 CS_ETM_ETMCR = CS_ETM_COMMON_BLK_MAX_V !! 36 CS_ETM_ETMCR = CS_ETM_CPU + 1,
58 CS_ETM_ETMTRACEIDR, 37 CS_ETM_ETMTRACEIDR,
59 /* RO, taken from sysFS */ 38 /* RO, taken from sysFS */
60 CS_ETM_ETMCCER, 39 CS_ETM_ETMCCER,
61 CS_ETM_ETMIDR, 40 CS_ETM_ETMIDR,
62 CS_ETM_PRIV_MAX, 41 CS_ETM_PRIV_MAX,
63 }; 42 };
64 43
65 /* define fixed version 0 length - allow new f <<
66 #define CS_ETM_NR_TRC_PARAMS_V0 (CS_ETM_ETMIDR <<
67 <<
68 /* ETMv4 metadata */ 44 /* ETMv4 metadata */
69 enum { 45 enum {
70 /* Dynamic, configurable parameters */ 46 /* Dynamic, configurable parameters */
71 CS_ETMV4_TRCCONFIGR = CS_ETM_COMMON_BL !! 47 CS_ETMV4_TRCCONFIGR = CS_ETM_CPU + 1,
72 CS_ETMV4_TRCTRACEIDR, 48 CS_ETMV4_TRCTRACEIDR,
73 /* RO, taken from sysFS */ 49 /* RO, taken from sysFS */
74 CS_ETMV4_TRCIDR0, 50 CS_ETMV4_TRCIDR0,
75 CS_ETMV4_TRCIDR1, 51 CS_ETMV4_TRCIDR1,
76 CS_ETMV4_TRCIDR2, 52 CS_ETMV4_TRCIDR2,
77 CS_ETMV4_TRCIDR8, 53 CS_ETMV4_TRCIDR8,
78 CS_ETMV4_TRCAUTHSTATUS, 54 CS_ETMV4_TRCAUTHSTATUS,
79 CS_ETMV4_TS_SOURCE, <<
80 CS_ETMV4_PRIV_MAX, 55 CS_ETMV4_PRIV_MAX,
81 }; 56 };
82 57
83 /* define fixed version 0 length - allow new f <<
84 #define CS_ETMV4_NR_TRC_PARAMS_V0 (CS_ETMV4_TR <<
85 <<
86 /* <<
87 * ETE metadata is ETMv4 plus TRCDEVARCH regis <<
88 * added in header V1 <<
89 */ <<
90 enum { <<
91 /* Dynamic, configurable parameters */ <<
92 CS_ETE_TRCCONFIGR = CS_ETM_COMMON_BLK_ <<
93 CS_ETE_TRCTRACEIDR, <<
94 /* RO, taken from sysFS */ <<
95 CS_ETE_TRCIDR0, <<
96 CS_ETE_TRCIDR1, <<
97 CS_ETE_TRCIDR2, <<
98 CS_ETE_TRCIDR8, <<
99 CS_ETE_TRCAUTHSTATUS, <<
100 CS_ETE_TRCDEVARCH, <<
101 CS_ETE_TS_SOURCE, <<
102 CS_ETE_PRIV_MAX <<
103 }; <<
104 <<
105 /* <<
106 * Check for valid CoreSight trace ID. If an i <<
107 * then IDs are present in the hardware ID pac <<
108 */ <<
109 #define CS_IS_VALID_TRACE_ID(id) ((id > 0) && <<
110 <<
111 /* 58 /*
112 * ETMv3 exception encoding number: 59 * ETMv3 exception encoding number:
113 * See Embedded Trace Macrocell specification !! 60 * See Embedded Trace Macrocell spcification (ARM IHI 0014Q)
114 * table 7-12 Encoding of Exception[3:0] for n 61 * table 7-12 Encoding of Exception[3:0] for non-ARMv7-M processors.
115 */ 62 */
116 enum { 63 enum {
117 CS_ETMV3_EXC_NONE = 0, 64 CS_ETMV3_EXC_NONE = 0,
118 CS_ETMV3_EXC_DEBUG_HALT = 1, 65 CS_ETMV3_EXC_DEBUG_HALT = 1,
119 CS_ETMV3_EXC_SMC = 2, 66 CS_ETMV3_EXC_SMC = 2,
120 CS_ETMV3_EXC_HYP = 3, 67 CS_ETMV3_EXC_HYP = 3,
121 CS_ETMV3_EXC_ASYNC_DATA_ABORT = 4, 68 CS_ETMV3_EXC_ASYNC_DATA_ABORT = 4,
122 CS_ETMV3_EXC_JAZELLE_THUMBEE = 5, 69 CS_ETMV3_EXC_JAZELLE_THUMBEE = 5,
123 CS_ETMV3_EXC_PE_RESET = 8, 70 CS_ETMV3_EXC_PE_RESET = 8,
124 CS_ETMV3_EXC_UNDEFINED_INSTR = 9, 71 CS_ETMV3_EXC_UNDEFINED_INSTR = 9,
125 CS_ETMV3_EXC_SVC = 10, 72 CS_ETMV3_EXC_SVC = 10,
126 CS_ETMV3_EXC_PREFETCH_ABORT = 11, 73 CS_ETMV3_EXC_PREFETCH_ABORT = 11,
127 CS_ETMV3_EXC_DATA_FAULT = 12, 74 CS_ETMV3_EXC_DATA_FAULT = 12,
128 CS_ETMV3_EXC_GENERIC = 13, 75 CS_ETMV3_EXC_GENERIC = 13,
129 CS_ETMV3_EXC_IRQ = 14, 76 CS_ETMV3_EXC_IRQ = 14,
130 CS_ETMV3_EXC_FIQ = 15, 77 CS_ETMV3_EXC_FIQ = 15,
131 }; 78 };
132 79
133 /* 80 /*
134 * ETMv4 exception encoding number: 81 * ETMv4 exception encoding number:
135 * See ARM Embedded Trace Macrocell Architectu 82 * See ARM Embedded Trace Macrocell Architecture Specification (ARM IHI 0064D)
136 * table 6-12 Possible values for the TYPE fie 83 * table 6-12 Possible values for the TYPE field in an Exception instruction
137 * trace packet, for ARMv7-A/R and ARMv8-A/R P 84 * trace packet, for ARMv7-A/R and ARMv8-A/R PEs.
138 */ 85 */
139 enum { 86 enum {
140 CS_ETMV4_EXC_RESET = 0, 87 CS_ETMV4_EXC_RESET = 0,
141 CS_ETMV4_EXC_DEBUG_HALT = 1, 88 CS_ETMV4_EXC_DEBUG_HALT = 1,
142 CS_ETMV4_EXC_CALL = 2, 89 CS_ETMV4_EXC_CALL = 2,
143 CS_ETMV4_EXC_TRAP = 3, 90 CS_ETMV4_EXC_TRAP = 3,
144 CS_ETMV4_EXC_SYSTEM_ERROR = 4, 91 CS_ETMV4_EXC_SYSTEM_ERROR = 4,
145 CS_ETMV4_EXC_INST_DEBUG = 6, 92 CS_ETMV4_EXC_INST_DEBUG = 6,
146 CS_ETMV4_EXC_DATA_DEBUG = 7, 93 CS_ETMV4_EXC_DATA_DEBUG = 7,
147 CS_ETMV4_EXC_ALIGNMENT = 10, 94 CS_ETMV4_EXC_ALIGNMENT = 10,
148 CS_ETMV4_EXC_INST_FAULT = 11, 95 CS_ETMV4_EXC_INST_FAULT = 11,
149 CS_ETMV4_EXC_DATA_FAULT = 12, 96 CS_ETMV4_EXC_DATA_FAULT = 12,
150 CS_ETMV4_EXC_IRQ = 14, 97 CS_ETMV4_EXC_IRQ = 14,
151 CS_ETMV4_EXC_FIQ = 15, 98 CS_ETMV4_EXC_FIQ = 15,
152 CS_ETMV4_EXC_END = 31, 99 CS_ETMV4_EXC_END = 31,
153 }; 100 };
154 101
155 enum cs_etm_sample_type { 102 enum cs_etm_sample_type {
156 CS_ETM_EMPTY, 103 CS_ETM_EMPTY,
157 CS_ETM_RANGE, 104 CS_ETM_RANGE,
158 CS_ETM_DISCONTINUITY, 105 CS_ETM_DISCONTINUITY,
159 CS_ETM_EXCEPTION, 106 CS_ETM_EXCEPTION,
160 CS_ETM_EXCEPTION_RET, 107 CS_ETM_EXCEPTION_RET,
161 }; 108 };
162 109
163 enum cs_etm_isa { 110 enum cs_etm_isa {
164 CS_ETM_ISA_UNKNOWN, 111 CS_ETM_ISA_UNKNOWN,
165 CS_ETM_ISA_A64, 112 CS_ETM_ISA_A64,
166 CS_ETM_ISA_A32, 113 CS_ETM_ISA_A32,
167 CS_ETM_ISA_T32, 114 CS_ETM_ISA_T32,
168 }; 115 };
169 116
170 struct cs_etm_queue; 117 struct cs_etm_queue;
171 118
172 struct cs_etm_packet { 119 struct cs_etm_packet {
173 enum cs_etm_sample_type sample_type; 120 enum cs_etm_sample_type sample_type;
174 enum cs_etm_isa isa; 121 enum cs_etm_isa isa;
175 u64 start_addr; 122 u64 start_addr;
176 u64 end_addr; 123 u64 end_addr;
177 u32 instr_count; 124 u32 instr_count;
178 u32 last_instr_type; 125 u32 last_instr_type;
179 u32 last_instr_subtype; 126 u32 last_instr_subtype;
180 u32 flags; 127 u32 flags;
181 u32 exception_number; 128 u32 exception_number;
182 bool last_instr_cond; !! 129 u8 last_instr_cond;
183 bool last_instr_taken_branch; !! 130 u8 last_instr_taken_branch;
184 u8 last_instr_size; 131 u8 last_instr_size;
185 u8 trace_chan_id; 132 u8 trace_chan_id;
186 int cpu; 133 int cpu;
187 }; 134 };
188 135
189 #define CS_ETM_PACKET_MAX_BUFFER 1024 136 #define CS_ETM_PACKET_MAX_BUFFER 1024
190 137
191 /* 138 /*
192 * When working with per-thread scenarios the 139 * When working with per-thread scenarios the process under trace can
193 * be scheduled on any CPU and as such, more t 140 * be scheduled on any CPU and as such, more than one traceID may be
194 * associated with the same process. Since a 141 * associated with the same process. Since a traceID of '' is illegal
195 * as per the CoreSight architecture, use that 142 * as per the CoreSight architecture, use that specific value to
196 * identify the queue where all packets (with 143 * identify the queue where all packets (with any traceID) are
197 * aggregated. 144 * aggregated.
198 */ 145 */
199 #define CS_ETM_PER_THREAD_TRACEID 0 146 #define CS_ETM_PER_THREAD_TRACEID 0
200 147
201 struct cs_etm_packet_queue { 148 struct cs_etm_packet_queue {
202 u32 packet_count; 149 u32 packet_count;
203 u32 head; 150 u32 head;
204 u32 tail; 151 u32 tail;
205 u32 instr_count; 152 u32 instr_count;
206 u64 cs_timestamp; /* Timestamp from tr !! 153 u64 timestamp;
207 u64 next_cs_timestamp; !! 154 u64 next_timestamp;
208 struct cs_etm_packet packet_buffer[CS_ 155 struct cs_etm_packet packet_buffer[CS_ETM_PACKET_MAX_BUFFER];
209 }; 156 };
210 157
211 #define KiB(x) ((x) * 1024) 158 #define KiB(x) ((x) * 1024)
212 #define MiB(x) ((x) * 1024 * 1024) 159 #define MiB(x) ((x) * 1024 * 1024)
213 160
214 #define CS_ETM_INVAL_ADDR 0xdeadbeefdeadbeefUL 161 #define CS_ETM_INVAL_ADDR 0xdeadbeefdeadbeefUL
215 162
216 #define BMVAL(val, lsb, msb) ((val & GENMAS 163 #define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb)
217 164
218 #define CS_ETM_HEADER_SIZE (CS_HEADER_VERSION_ !! 165 #define CS_ETM_HEADER_SIZE (CS_HEADER_VERSION_0_MAX * sizeof(u64))
219 166
220 #define __perf_cs_etmv3_magic 0x30303030303030 167 #define __perf_cs_etmv3_magic 0x3030303030303030ULL
221 #define __perf_cs_etmv4_magic 0x40404040404040 168 #define __perf_cs_etmv4_magic 0x4040404040404040ULL
222 #define __perf_cs_ete_magic 0x50505050505050 <<
223 #define CS_ETMV3_PRIV_SIZE (CS_ETM_PRIV_MAX * 169 #define CS_ETMV3_PRIV_SIZE (CS_ETM_PRIV_MAX * sizeof(u64))
224 #define CS_ETMV4_PRIV_SIZE (CS_ETMV4_PRIV_MAX 170 #define CS_ETMV4_PRIV_SIZE (CS_ETMV4_PRIV_MAX * sizeof(u64))
225 #define CS_ETE_PRIV_SIZE (CS_ETE_PRIV_MAX * si <<
226 <<
227 #define INFO_HEADER_SIZE (sizeof(((struct perf <<
228 sizeof(((struct perf <<
229 <<
230 /* CoreSight trace ID is currently the bottom <<
231 #define CORESIGHT_TRACE_ID_VAL_MASK GENMAS <<
232 171
>> 172 #ifdef HAVE_CSTRACE_SUPPORT
233 int cs_etm__process_auxtrace_info(union perf_e 173 int cs_etm__process_auxtrace_info(union perf_event *event,
234 struct perf_ 174 struct perf_session *session);
235 void cs_etm_get_default_config(const struct pe !! 175 int cs_etm__get_cpu(u8 trace_chan_id, int *cpu);
236 !! 176 int cs_etm__etmq_set_tid(struct cs_etm_queue *etmq,
237 enum cs_etm_pid_fmt { !! 177 pid_t tid, u8 trace_chan_id);
238 CS_ETM_PIDFMT_NONE, <<
239 CS_ETM_PIDFMT_CTXTID, <<
240 CS_ETM_PIDFMT_CTXTID2 <<
241 }; <<
242 <<
243 #ifdef HAVE_CSTRACE_SUPPORT <<
244 #include <opencsd/ocsd_if_types.h> <<
245 int cs_etm__get_cpu(struct cs_etm_queue *etmq, <<
246 enum cs_etm_pid_fmt cs_etm__get_pid_fmt(struct <<
247 int cs_etm__etmq_set_tid_el(struct cs_etm_queu <<
248 u8 trace_chan_id, <<
249 bool cs_etm__etmq_is_timeless(struct cs_etm_qu 178 bool cs_etm__etmq_is_timeless(struct cs_etm_queue *etmq);
250 void cs_etm__etmq_set_traceid_queue_timestamp( 179 void cs_etm__etmq_set_traceid_queue_timestamp(struct cs_etm_queue *etmq,
251 180 u8 trace_chan_id);
252 struct cs_etm_packet_queue 181 struct cs_etm_packet_queue
253 *cs_etm__etmq_get_packet_queue(struct cs_etm_q 182 *cs_etm__etmq_get_packet_queue(struct cs_etm_queue *etmq, u8 trace_chan_id);
254 int cs_etm__process_auxtrace_info_full(union p <<
255 struct <<
256 u64 cs_etm__convert_sample_time(struct cs_etm_ <<
257 #else 183 #else
258 static inline int 184 static inline int
259 cs_etm__process_auxtrace_info_full(union perf_ !! 185 cs_etm__process_auxtrace_info(union perf_event *event __maybe_unused,
260 struct perf !! 186 struct perf_session *session __maybe_unused)
>> 187 {
>> 188 return -1;
>> 189 }
>> 190
>> 191 static inline int cs_etm__get_cpu(u8 trace_chan_id __maybe_unused,
>> 192 int *cpu __maybe_unused)
>> 193 {
>> 194 return -1;
>> 195 }
>> 196
>> 197 static inline int cs_etm__etmq_set_tid(
>> 198 struct cs_etm_queue *etmq __maybe_unused,
>> 199 pid_t tid __maybe_unused,
>> 200 u8 trace_chan_id __maybe_unused)
261 { 201 {
262 pr_err("\nCS ETM Trace: OpenCSD is not <<
263 return -1; 202 return -1;
>> 203 }
>> 204
>> 205 static inline bool cs_etm__etmq_is_timeless(
>> 206 struct cs_etm_queue *etmq __maybe_unused)
>> 207 {
>> 208 /* What else to return? */
>> 209 return true;
>> 210 }
>> 211
>> 212 static inline void cs_etm__etmq_set_traceid_queue_timestamp(
>> 213 struct cs_etm_queue *etmq __maybe_unused,
>> 214 u8 trace_chan_id __maybe_unused) {}
>> 215
>> 216 static inline struct cs_etm_packet_queue *cs_etm__etmq_get_packet_queue(
>> 217 struct cs_etm_queue *etmq __maybe_unused,
>> 218 u8 trace_chan_id __maybe_unused)
>> 219 {
>> 220 return NULL;
264 } 221 }
265 #endif 222 #endif
266 223
267 #endif 224 #endif
268 225
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