1 /* SPDX-License-Identifier: GPL-2.0 */ 1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* 2 /*
3 * Copyright(C) 2015 Linaro Limited. All right 3 * Copyright(C) 2015 Linaro Limited. All rights reserved.
4 * Author: Mathieu Poirier <mathieu.poirier@li 4 * Author: Mathieu Poirier <mathieu.poirier@linaro.org>
5 */ 5 */
6 6
7 #ifndef INCLUDE__UTIL_PERF_CS_ETM_H__ 7 #ifndef INCLUDE__UTIL_PERF_CS_ETM_H__
8 #define INCLUDE__UTIL_PERF_CS_ETM_H__ 8 #define INCLUDE__UTIL_PERF_CS_ETM_H__
9 9
10 #include "debug.h" <<
11 #include "util/event.h" 10 #include "util/event.h"
12 #include <linux/bits.h> !! 11 #include "util/session.h"
13 12
14 struct perf_session; !! 13 /* Versionning header in case things need tro change in the future. That way
15 struct perf_pmu; <<
16 <<
17 /* <<
18 * Versioning header in case things need to ch <<
19 * decoding of old snapshot is still possible. 14 * decoding of old snapshot is still possible.
20 */ 15 */
21 enum { 16 enum {
22 /* Starting with 0x0 */ 17 /* Starting with 0x0 */
23 CS_HEADER_VERSION, !! 18 CS_HEADER_VERSION_0,
24 /* PMU->type (32 bit), total # of CPUs 19 /* PMU->type (32 bit), total # of CPUs (32 bit) */
25 CS_PMU_TYPE_CPUS, 20 CS_PMU_TYPE_CPUS,
26 CS_ETM_SNAPSHOT, 21 CS_ETM_SNAPSHOT,
27 CS_HEADER_VERSION_MAX, !! 22 CS_HEADER_VERSION_0_MAX,
28 }; 23 };
29 24
30 /* <<
31 * Update the version for new format. <<
32 * <<
33 * Version 1: format adds a param count to the <<
34 * This allows easy adding of new metadata par <<
35 * Requires that new params always added after <<
36 * Also allows client reader to handle file ve <<
37 * checking the number of params in the file v <<
38 * <<
39 * Version 2: Drivers will use PERF_RECORD_AUX <<
40 * CoreSight Trace ID. ...TRACEIDR metadata wi <<
41 * but with addition flags. <<
42 */ <<
43 #define CS_HEADER_CURRENT_VERSION 2 <<
44 <<
45 /* Beginning of header common to both ETMv3 an 25 /* Beginning of header common to both ETMv3 and V4 */
46 enum { 26 enum {
47 CS_ETM_MAGIC, 27 CS_ETM_MAGIC,
48 CS_ETM_CPU, 28 CS_ETM_CPU,
49 /* Number of trace config params in fo <<
50 CS_ETM_NR_TRC_PARAMS, <<
51 CS_ETM_COMMON_BLK_MAX_V1, <<
52 }; 29 };
53 30
54 /* ETMv3/PTM metadata */ 31 /* ETMv3/PTM metadata */
55 enum { 32 enum {
56 /* Dynamic, configurable parameters */ 33 /* Dynamic, configurable parameters */
57 CS_ETM_ETMCR = CS_ETM_COMMON_BLK_MAX_V !! 34 CS_ETM_ETMCR = CS_ETM_CPU + 1,
58 CS_ETM_ETMTRACEIDR, 35 CS_ETM_ETMTRACEIDR,
59 /* RO, taken from sysFS */ 36 /* RO, taken from sysFS */
60 CS_ETM_ETMCCER, 37 CS_ETM_ETMCCER,
61 CS_ETM_ETMIDR, 38 CS_ETM_ETMIDR,
62 CS_ETM_PRIV_MAX, 39 CS_ETM_PRIV_MAX,
63 }; 40 };
64 41
65 /* define fixed version 0 length - allow new f <<
66 #define CS_ETM_NR_TRC_PARAMS_V0 (CS_ETM_ETMIDR <<
67 <<
68 /* ETMv4 metadata */ 42 /* ETMv4 metadata */
69 enum { 43 enum {
70 /* Dynamic, configurable parameters */ 44 /* Dynamic, configurable parameters */
71 CS_ETMV4_TRCCONFIGR = CS_ETM_COMMON_BL !! 45 CS_ETMV4_TRCCONFIGR = CS_ETM_CPU + 1,
72 CS_ETMV4_TRCTRACEIDR, 46 CS_ETMV4_TRCTRACEIDR,
73 /* RO, taken from sysFS */ 47 /* RO, taken from sysFS */
74 CS_ETMV4_TRCIDR0, 48 CS_ETMV4_TRCIDR0,
75 CS_ETMV4_TRCIDR1, 49 CS_ETMV4_TRCIDR1,
76 CS_ETMV4_TRCIDR2, 50 CS_ETMV4_TRCIDR2,
77 CS_ETMV4_TRCIDR8, 51 CS_ETMV4_TRCIDR8,
78 CS_ETMV4_TRCAUTHSTATUS, 52 CS_ETMV4_TRCAUTHSTATUS,
79 CS_ETMV4_TS_SOURCE, <<
80 CS_ETMV4_PRIV_MAX, 53 CS_ETMV4_PRIV_MAX,
81 }; 54 };
82 55
83 /* define fixed version 0 length - allow new f <<
84 #define CS_ETMV4_NR_TRC_PARAMS_V0 (CS_ETMV4_TR <<
85 <<
86 /* <<
87 * ETE metadata is ETMv4 plus TRCDEVARCH regis <<
88 * added in header V1 <<
89 */ <<
90 enum { <<
91 /* Dynamic, configurable parameters */ <<
92 CS_ETE_TRCCONFIGR = CS_ETM_COMMON_BLK_ <<
93 CS_ETE_TRCTRACEIDR, <<
94 /* RO, taken from sysFS */ <<
95 CS_ETE_TRCIDR0, <<
96 CS_ETE_TRCIDR1, <<
97 CS_ETE_TRCIDR2, <<
98 CS_ETE_TRCIDR8, <<
99 CS_ETE_TRCAUTHSTATUS, <<
100 CS_ETE_TRCDEVARCH, <<
101 CS_ETE_TS_SOURCE, <<
102 CS_ETE_PRIV_MAX <<
103 }; <<
104 <<
105 /* <<
106 * Check for valid CoreSight trace ID. If an i <<
107 * then IDs are present in the hardware ID pac <<
108 */ <<
109 #define CS_IS_VALID_TRACE_ID(id) ((id > 0) && <<
110 <<
111 /* 56 /*
112 * ETMv3 exception encoding number: 57 * ETMv3 exception encoding number:
113 * See Embedded Trace Macrocell specification !! 58 * See Embedded Trace Macrocell spcification (ARM IHI 0014Q)
114 * table 7-12 Encoding of Exception[3:0] for n 59 * table 7-12 Encoding of Exception[3:0] for non-ARMv7-M processors.
115 */ 60 */
116 enum { 61 enum {
117 CS_ETMV3_EXC_NONE = 0, 62 CS_ETMV3_EXC_NONE = 0,
118 CS_ETMV3_EXC_DEBUG_HALT = 1, 63 CS_ETMV3_EXC_DEBUG_HALT = 1,
119 CS_ETMV3_EXC_SMC = 2, 64 CS_ETMV3_EXC_SMC = 2,
120 CS_ETMV3_EXC_HYP = 3, 65 CS_ETMV3_EXC_HYP = 3,
121 CS_ETMV3_EXC_ASYNC_DATA_ABORT = 4, 66 CS_ETMV3_EXC_ASYNC_DATA_ABORT = 4,
122 CS_ETMV3_EXC_JAZELLE_THUMBEE = 5, 67 CS_ETMV3_EXC_JAZELLE_THUMBEE = 5,
123 CS_ETMV3_EXC_PE_RESET = 8, 68 CS_ETMV3_EXC_PE_RESET = 8,
124 CS_ETMV3_EXC_UNDEFINED_INSTR = 9, 69 CS_ETMV3_EXC_UNDEFINED_INSTR = 9,
125 CS_ETMV3_EXC_SVC = 10, 70 CS_ETMV3_EXC_SVC = 10,
126 CS_ETMV3_EXC_PREFETCH_ABORT = 11, 71 CS_ETMV3_EXC_PREFETCH_ABORT = 11,
127 CS_ETMV3_EXC_DATA_FAULT = 12, 72 CS_ETMV3_EXC_DATA_FAULT = 12,
128 CS_ETMV3_EXC_GENERIC = 13, 73 CS_ETMV3_EXC_GENERIC = 13,
129 CS_ETMV3_EXC_IRQ = 14, 74 CS_ETMV3_EXC_IRQ = 14,
130 CS_ETMV3_EXC_FIQ = 15, 75 CS_ETMV3_EXC_FIQ = 15,
131 }; 76 };
132 77
133 /* 78 /*
134 * ETMv4 exception encoding number: 79 * ETMv4 exception encoding number:
135 * See ARM Embedded Trace Macrocell Architectu 80 * See ARM Embedded Trace Macrocell Architecture Specification (ARM IHI 0064D)
136 * table 6-12 Possible values for the TYPE fie 81 * table 6-12 Possible values for the TYPE field in an Exception instruction
137 * trace packet, for ARMv7-A/R and ARMv8-A/R P 82 * trace packet, for ARMv7-A/R and ARMv8-A/R PEs.
138 */ 83 */
139 enum { 84 enum {
140 CS_ETMV4_EXC_RESET = 0, 85 CS_ETMV4_EXC_RESET = 0,
141 CS_ETMV4_EXC_DEBUG_HALT = 1, 86 CS_ETMV4_EXC_DEBUG_HALT = 1,
142 CS_ETMV4_EXC_CALL = 2, 87 CS_ETMV4_EXC_CALL = 2,
143 CS_ETMV4_EXC_TRAP = 3, 88 CS_ETMV4_EXC_TRAP = 3,
144 CS_ETMV4_EXC_SYSTEM_ERROR = 4, 89 CS_ETMV4_EXC_SYSTEM_ERROR = 4,
145 CS_ETMV4_EXC_INST_DEBUG = 6, 90 CS_ETMV4_EXC_INST_DEBUG = 6,
146 CS_ETMV4_EXC_DATA_DEBUG = 7, 91 CS_ETMV4_EXC_DATA_DEBUG = 7,
147 CS_ETMV4_EXC_ALIGNMENT = 10, 92 CS_ETMV4_EXC_ALIGNMENT = 10,
148 CS_ETMV4_EXC_INST_FAULT = 11, 93 CS_ETMV4_EXC_INST_FAULT = 11,
149 CS_ETMV4_EXC_DATA_FAULT = 12, 94 CS_ETMV4_EXC_DATA_FAULT = 12,
150 CS_ETMV4_EXC_IRQ = 14, 95 CS_ETMV4_EXC_IRQ = 14,
151 CS_ETMV4_EXC_FIQ = 15, 96 CS_ETMV4_EXC_FIQ = 15,
152 CS_ETMV4_EXC_END = 31, 97 CS_ETMV4_EXC_END = 31,
153 }; 98 };
154 99
155 enum cs_etm_sample_type { !! 100 /* RB tree for quick conversion between traceID and metadata pointers */
156 CS_ETM_EMPTY, !! 101 struct intlist *traceid_list;
157 CS_ETM_RANGE, <<
158 CS_ETM_DISCONTINUITY, <<
159 CS_ETM_EXCEPTION, <<
160 CS_ETM_EXCEPTION_RET, <<
161 }; <<
162 <<
163 enum cs_etm_isa { <<
164 CS_ETM_ISA_UNKNOWN, <<
165 CS_ETM_ISA_A64, <<
166 CS_ETM_ISA_A32, <<
167 CS_ETM_ISA_T32, <<
168 }; <<
169 <<
170 struct cs_etm_queue; <<
171 <<
172 struct cs_etm_packet { <<
173 enum cs_etm_sample_type sample_type; <<
174 enum cs_etm_isa isa; <<
175 u64 start_addr; <<
176 u64 end_addr; <<
177 u32 instr_count; <<
178 u32 last_instr_type; <<
179 u32 last_instr_subtype; <<
180 u32 flags; <<
181 u32 exception_number; <<
182 bool last_instr_cond; <<
183 bool last_instr_taken_branch; <<
184 u8 last_instr_size; <<
185 u8 trace_chan_id; <<
186 int cpu; <<
187 }; <<
188 <<
189 #define CS_ETM_PACKET_MAX_BUFFER 1024 <<
190 <<
191 /* <<
192 * When working with per-thread scenarios the <<
193 * be scheduled on any CPU and as such, more t <<
194 * associated with the same process. Since a <<
195 * as per the CoreSight architecture, use that <<
196 * identify the queue where all packets (with <<
197 * aggregated. <<
198 */ <<
199 #define CS_ETM_PER_THREAD_TRACEID 0 <<
200 <<
201 struct cs_etm_packet_queue { <<
202 u32 packet_count; <<
203 u32 head; <<
204 u32 tail; <<
205 u32 instr_count; <<
206 u64 cs_timestamp; /* Timestamp from tr <<
207 u64 next_cs_timestamp; <<
208 struct cs_etm_packet packet_buffer[CS_ <<
209 }; <<
210 102
211 #define KiB(x) ((x) * 1024) 103 #define KiB(x) ((x) * 1024)
212 #define MiB(x) ((x) * 1024 * 1024) 104 #define MiB(x) ((x) * 1024 * 1024)
213 105
214 #define CS_ETM_INVAL_ADDR 0xdeadbeefdeadbeefUL !! 106 #define CS_ETM_HEADER_SIZE (CS_HEADER_VERSION_0_MAX * sizeof(u64))
215 <<
216 #define BMVAL(val, lsb, msb) ((val & GENMAS <<
217 <<
218 #define CS_ETM_HEADER_SIZE (CS_HEADER_VERSION_ <<
219 107
220 #define __perf_cs_etmv3_magic 0x30303030303030 108 #define __perf_cs_etmv3_magic 0x3030303030303030ULL
221 #define __perf_cs_etmv4_magic 0x40404040404040 109 #define __perf_cs_etmv4_magic 0x4040404040404040ULL
222 #define __perf_cs_ete_magic 0x50505050505050 <<
223 #define CS_ETMV3_PRIV_SIZE (CS_ETM_PRIV_MAX * 110 #define CS_ETMV3_PRIV_SIZE (CS_ETM_PRIV_MAX * sizeof(u64))
224 #define CS_ETMV4_PRIV_SIZE (CS_ETMV4_PRIV_MAX 111 #define CS_ETMV4_PRIV_SIZE (CS_ETMV4_PRIV_MAX * sizeof(u64))
225 #define CS_ETE_PRIV_SIZE (CS_ETE_PRIV_MAX * si <<
226 <<
227 #define INFO_HEADER_SIZE (sizeof(((struct perf <<
228 sizeof(((struct perf <<
229 <<
230 /* CoreSight trace ID is currently the bottom <<
231 #define CORESIGHT_TRACE_ID_VAL_MASK GENMAS <<
232 112
>> 113 #ifdef HAVE_CSTRACE_SUPPORT
233 int cs_etm__process_auxtrace_info(union perf_e 114 int cs_etm__process_auxtrace_info(union perf_event *event,
234 struct perf_ 115 struct perf_session *session);
235 void cs_etm_get_default_config(const struct pe !! 116 int cs_etm__get_cpu(u8 trace_chan_id, int *cpu);
236 <<
237 enum cs_etm_pid_fmt { <<
238 CS_ETM_PIDFMT_NONE, <<
239 CS_ETM_PIDFMT_CTXTID, <<
240 CS_ETM_PIDFMT_CTXTID2 <<
241 }; <<
242 <<
243 #ifdef HAVE_CSTRACE_SUPPORT <<
244 #include <opencsd/ocsd_if_types.h> <<
245 int cs_etm__get_cpu(struct cs_etm_queue *etmq, <<
246 enum cs_etm_pid_fmt cs_etm__get_pid_fmt(struct <<
247 int cs_etm__etmq_set_tid_el(struct cs_etm_queu <<
248 u8 trace_chan_id, <<
249 bool cs_etm__etmq_is_timeless(struct cs_etm_qu <<
250 void cs_etm__etmq_set_traceid_queue_timestamp( <<
251 <<
252 struct cs_etm_packet_queue <<
253 *cs_etm__etmq_get_packet_queue(struct cs_etm_q <<
254 int cs_etm__process_auxtrace_info_full(union p <<
255 struct <<
256 u64 cs_etm__convert_sample_time(struct cs_etm_ <<
257 #else 117 #else
258 static inline int 118 static inline int
259 cs_etm__process_auxtrace_info_full(union perf_ !! 119 cs_etm__process_auxtrace_info(union perf_event *event __maybe_unused,
260 struct perf !! 120 struct perf_session *session __maybe_unused)
>> 121 {
>> 122 return -1;
>> 123 }
>> 124
>> 125 static inline int cs_etm__get_cpu(u8 trace_chan_id __maybe_unused,
>> 126 int *cpu __maybe_unused)
261 { 127 {
262 pr_err("\nCS ETM Trace: OpenCSD is not <<
263 return -1; 128 return -1;
264 } 129 }
265 #endif 130 #endif
266 131
267 #endif 132 #endif
268 133
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