1 What: /sys/bus/coresight/devices/<memory_map>.etb/enable_sink 2 Date: November 2014 3 KernelVersion: 3.19 4 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 5 Description: (RW) Add/remove a sink from a trace path. There can be multiple 6 source for a single sink. 7 8 ex:: 9 10 echo 1 > /sys/bus/coresight/devices/20010000.etb/enable_sink 11 12 What: /sys/bus/coresight/devices/<memory_map>.etb/trigger_cntr 13 Date: November 2014 14 KernelVersion: 3.19 15 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 16 Description: (RW) Disables write access to the Trace RAM by stopping the 17 formatter after a defined number of words have been stored 18 following the trigger event. The number of 32-bit words written 19 into the Trace RAM following the trigger event is equal to the 20 value stored in this register+1 (from ARM ETB-TRM). 21 22 What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/rdp 23 Date: March 2016 24 KernelVersion: 4.7 25 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 26 Description: (Read) Defines the depth, in words, of the trace RAM in powers of 27 2. The value is read directly from HW register RDP, 0x004. 28 29 What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/sts 30 Date: March 2016 31 KernelVersion: 4.7 32 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 33 Description: (Read) Shows the value held by the ETB status register. The value 34 is read directly from HW register STS, 0x00C. 35 36 What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/rrp 37 Date: March 2016 38 KernelVersion: 4.7 39 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 40 Description: (Read) Shows the value held by the ETB RAM Read Pointer register 41 that is used to read entries from the Trace RAM over the APB 42 interface. The value is read directly from HW register RRP, 43 0x014. 44 45 What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/rwp 46 Date: March 2016 47 KernelVersion: 4.7 48 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 49 Description: (Read) Shows the value held by the ETB RAM Write Pointer register 50 that is used to sets the write pointer to write entries from 51 the CoreSight bus into the Trace RAM. The value is read directly 52 from HW register RWP, 0x018. 53 54 What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/trg 55 Date: March 2016 56 KernelVersion: 4.7 57 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 58 Description: (Read) Similar to "trigger_cntr" above except that this value is 59 read directly from HW register TRG, 0x01C. 60 61 What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/ctl 62 Date: March 2016 63 KernelVersion: 4.7 64 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 65 Description: (Read) Shows the value held by the ETB Control register. The value 66 is read directly from HW register CTL, 0x020. 67 68 What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/ffsr 69 Date: March 2016 70 KernelVersion: 4.7 71 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 72 Description: (Read) Shows the value held by the ETB Formatter and Flush Status 73 register. The value is read directly from HW register FFSR, 74 0x300. 75 76 What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/ffcr 77 Date: March 2016 78 KernelVersion: 4.7 79 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 80 Description: (Read) Shows the value held by the ETB Formatter and Flush Control 81 register. The value is read directly from HW register FFCR, 82 0x304.
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