1 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/enable_source 2 Date: November 2014 3 KernelVersion: 3.19 4 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 5 Description: (RW) Enable/disable tracing on this specific trace entiry. 6 Enabling a source implies the source has been configured 7 properly and a sink has been identidifed for it. The path 8 of coresight components linking the source to the sink is 9 configured and managed automatically by the coresight framework. 10 11 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_idx 12 Date: November 2014 13 KernelVersion: 3.19 14 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 15 Description: Select which address comparator or pair (of comparators) to 16 work with. 17 18 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_acctype 19 Date: November 2014 20 KernelVersion: 3.19 21 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 22 Description: (RW) Used in conjunction with @addr_idx. Specifies 23 characteristics about the address comparator being configure, 24 for example the access type, the kind of instruction to trace, 25 processor context ID to trigger on, etc. Individual fields in 26 the access type register may vary on the version of the trace 27 entity. 28 29 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_range 30 Date: November 2014 31 KernelVersion: 3.19 32 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 33 Description: (RW) Used in conjunction with @addr_idx. Specifies the range of 34 addresses to trigger on. Inclusion or exclusion is specified 35 in the corresponding access type register. 36 37 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_single 38 Date: November 2014 39 KernelVersion: 3.19 40 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 41 Description: (RW) Used in conjunction with @addr_idx. Specifies the single 42 address to trigger on, highly influenced by the configuration 43 options of the corresponding access type register. 44 45 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_start 46 Date: November 2014 47 KernelVersion: 3.19 48 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 49 Description: (RW) Used in conjunction with @addr_idx. Specifies the single 50 address to start tracing on, highly influenced by the 51 configuration options of the corresponding access type register. 52 53 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_stop 54 Date: November 2014 55 KernelVersion: 3.19 56 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 57 Description: (RW) Used in conjunction with @addr_idx. Specifies the single 58 address to stop tracing on, highly influenced by the 59 configuration options of the corresponding access type register. 60 61 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cntr_idx 62 Date: November 2014 63 KernelVersion: 3.19 64 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 65 Description: (RW) Specifies the counter to work on. 66 67 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cntr_event 68 Date: November 2014 69 KernelVersion: 3.19 70 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 71 Description: (RW) Used in conjunction with cntr_idx, give access to the 72 counter event register. 73 74 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cntr_val 75 Date: November 2014 76 KernelVersion: 3.19 77 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 78 Description: (RW) Used in conjunction with cntr_idx, give access to the 79 counter value register. 80 81 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cntr_rld_val 82 Date: November 2014 83 KernelVersion: 3.19 84 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 85 Description: (RW) Used in conjunction with cntr_idx, give access to the 86 counter reload value register. 87 88 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cntr_rld_event 89 Date: November 2014 90 KernelVersion: 3.19 91 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 92 Description: (RW) Used in conjunction with cntr_idx, give access to the 93 counter reload event register. 94 95 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/ctxid_idx 96 Date: November 2014 97 KernelVersion: 3.19 98 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 99 Description: (RW) Specifies the index of the context ID register to be 100 selected. 101 102 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/ctxid_mask 103 Date: November 2014 104 KernelVersion: 3.19 105 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 106 Description: (RW) Mask to apply to all the context ID comparator. 107 108 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/ctxid_pid 109 Date: November 2014 110 KernelVersion: 3.19 111 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 112 Description: (RW) Used with the ctxid_idx, specify with context ID to trigger 113 on. 114 115 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/enable_event 116 Date: November 2014 117 KernelVersion: 3.19 118 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 119 Description: (RW) Defines which event triggers a trace. 120 121 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/etmsr 122 Date: November 2014 123 KernelVersion: 3.19 124 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 125 Description: (RW) Gives access to the ETM status register, which holds 126 programming information and status on certains events. 127 128 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/fifofull_level 129 Date: November 2014 130 KernelVersion: 3.19 131 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 132 Description: (RW) Number of byte left in the fifo before considering it full. 133 Depending on the tracer's version, can also hold threshold for 134 data suppression. 135 136 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mode 137 Date: November 2014 138 KernelVersion: 3.19 139 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 140 Description: (RW) Interface with the driver's 'mode' field, controlling 141 various aspect of the trace entity such as time stamping, 142 context ID size and cycle accurate tracing. Driver specific 143 and bound to change depending on the driver. 144 145 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/nr_addr_cmp 146 Date: November 2014 147 KernelVersion: 3.19 148 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 149 Description: (Read) Provides the number of address comparators pairs accessible 150 on a trace unit, as specified by bit 3:0 of register ETMCCR. 151 152 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/nr_cntr 153 Date: November 2014 154 KernelVersion: 3.19 155 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 156 Description: (Read) Provides the number of counters accessible on a trace unit, 157 as specified by bit 15:13 of register ETMCCR. 158 159 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/nr_ctxid_cmp 160 Date: November 2014 161 KernelVersion: 3.19 162 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 163 Description: (Read) Provides the number of context ID comparator available on a 164 trace unit, as specified by bit 25:24 of register ETMCCR. 165 166 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/reset 167 Date: November 2014 168 KernelVersion: 3.19 169 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 170 Description: (Write) Cancels all configuration on a trace unit and set it back 171 to its boot configuration. 172 173 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/seq_12_event 174 Date: November 2014 175 KernelVersion: 3.19 176 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 177 Description: (RW) Defines the event that causes the sequencer to transition 178 from state 1 to state 2. 179 180 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/seq_13_event 181 Date: November 2014 182 KernelVersion: 3.19 183 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 184 Description: (RW) Defines the event that causes the sequencer to transition 185 from state 1 to state 3. 186 187 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/seq_21_event 188 Date: November 2014 189 KernelVersion: 3.19 190 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 191 Description: (RW) Defines the event that causes the sequencer to transition 192 from state 2 to state 1. 193 194 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/seq_23_event 195 Date: November 2014 196 KernelVersion: 3.19 197 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 198 Description: (RW) Defines the event that causes the sequencer to transition 199 from state 2 to state 3. 200 201 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/seq_31_event 202 Date: November 2014 203 KernelVersion: 3.19 204 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 205 Description: (RW) Defines the event that causes the sequencer to transition 206 from state 3 to state 1. 207 208 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/seq_32_event 209 Date: November 2014 210 KernelVersion: 3.19 211 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 212 Description: (RW) Defines the event that causes the sequencer to transition 213 from state 3 to state 2. 214 215 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/curr_seq_state 216 Date: November 2014 217 KernelVersion: 3.19 218 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 219 Description: (Read) Holds the current state of the sequencer. 220 221 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/sync_freq 222 Date: November 2014 223 KernelVersion: 3.19 224 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 225 Description: (RW) Holds the trace synchronization frequency value - must be 226 programmed with the various implementation behavior in mind. 227 228 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/timestamp_event 229 Date: November 2014 230 KernelVersion: 3.19 231 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 232 Description: (RW) Defines an event that requests the insertion of a timestamp 233 into the trace stream. 234 235 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/traceid 236 Date: November 2014 237 KernelVersion: 3.19 238 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 239 Description: (RO) Holds the trace ID that will appear in the trace stream 240 coming from this trace entity. 241 242 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/trigger_event 243 Date: November 2014 244 KernelVersion: 3.19 245 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 246 Description: (RW) Define the event that controls the trigger. 247 248 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cpu 249 Date: October 2015 250 KernelVersion: 4.4 251 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 252 Description: (RO) Holds the cpu number this tracer is affined to. 253 254 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmccr 255 Date: September 2015 256 KernelVersion: 4.4 257 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 258 Description: (RO) Print the content of the ETM Configuration Code register 259 (0x004). The value is read directly from the HW. 260 261 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmccer 262 Date: September 2015 263 KernelVersion: 4.4 264 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 265 Description: (RO) Print the content of the ETM Configuration Code Extension 266 register (0x1e8). The value is read directly from the HW. 267 268 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmscr 269 Date: September 2015 270 KernelVersion: 4.4 271 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 272 Description: (RO) Print the content of the ETM System Configuration 273 register (0x014). The value is read directly from the HW. 274 275 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmidr 276 Date: September 2015 277 KernelVersion: 4.4 278 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 279 Description: (RO) Print the content of the ETM ID register (0x1e4). The 280 value is read directly from the HW. 281 282 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmcr 283 Date: September 2015 284 KernelVersion: 4.4 285 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 286 Description: (RO) Print the content of the ETM Main Control register (0x000). 287 The value is read directly from the HW. 288 289 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmtraceidr 290 Date: September 2015 291 KernelVersion: 4.4 292 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 293 Description: (RO) Print the content of the ETM Trace ID register (0x200). 294 The value is read directly from the HW. 295 296 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmteevr 297 Date: September 2015 298 KernelVersion: 4.4 299 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 300 Description: (RO) Print the content of the ETM Trace Enable Event register 301 (0x020). The value is read directly from the HW. 302 303 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmtsscr 304 Date: September 2015 305 KernelVersion: 4.4 306 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 307 Description: (RO) Print the content of the ETM Trace Start/Stop Control 308 register (0x018). The value is read directly from the HW. 309 310 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmtecr1 311 Date: September 2015 312 KernelVersion: 4.4 313 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 314 Description: (RO) Print the content of the ETM Enable Control #1 315 register (0x024). The value is read directly from the HW. 316 317 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmtecr2 318 Date: September 2015 319 KernelVersion: 4.4 320 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 321 Description: (RO) Print the content of the ETM Enable Control #2 322 register (0x01c). The value is read directly from the HW.
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