1 What: /sys/bus/coresight/devices/etm<N>/enable_source 2 Date: April 2015 3 KernelVersion: 4.01 4 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 5 Description: (RW) Enable/disable tracing on this specific trace entiry. 6 Enabling a source implies the source has been configured 7 properly and a sink has been identidifed for it. The path 8 of coresight components linking the source to the sink is 9 configured and managed automatically by the coresight framework. 10 11 What: /sys/bus/coresight/devices/etm<N>/cpu 12 Date: April 2015 13 KernelVersion: 4.01 14 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 15 Description: (Read) The CPU this tracing entity is associated with. 16 17 What: /sys/bus/coresight/devices/etm<N>/nr_pe_cmp 18 Date: April 2015 19 KernelVersion: 4.01 20 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 21 Description: (Read) Indicates the number of PE comparator inputs that are 22 available for tracing. 23 24 What: /sys/bus/coresight/devices/etm<N>/nr_addr_cmp 25 Date: April 2015 26 KernelVersion: 4.01 27 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 28 Description: (Read) Indicates the number of address comparator pairs that are 29 available for tracing. 30 31 What: /sys/bus/coresight/devices/etm<N>/nr_cntr 32 Date: April 2015 33 KernelVersion: 4.01 34 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 35 Description: (Read) Indicates the number of counters that are available for 36 tracing. 37 38 What: /sys/bus/coresight/devices/etm<N>/nr_ext_inp 39 Date: April 2015 40 KernelVersion: 4.01 41 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 42 Description: (Read) Indicates how many external inputs are implemented. 43 44 What: /sys/bus/coresight/devices/etm<N>/numcidc 45 Date: April 2015 46 KernelVersion: 4.01 47 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 48 Description: (Read) Indicates the number of Context ID comparators that are 49 available for tracing. 50 51 What: /sys/bus/coresight/devices/etm<N>/numvmidc 52 Date: April 2015 53 KernelVersion: 4.01 54 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 55 Description: (Read) Indicates the number of VMID comparators that are available 56 for tracing. 57 58 What: /sys/bus/coresight/devices/etm<N>/nrseqstate 59 Date: April 2015 60 KernelVersion: 4.01 61 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 62 Description: (Read) Indicates the number of sequencer states that are 63 implemented. 64 65 What: /sys/bus/coresight/devices/etm<N>/nr_resource 66 Date: April 2015 67 KernelVersion: 4.01 68 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 69 Description: (Read) Indicates the number of resource selection pairs that are 70 available for tracing. 71 72 What: /sys/bus/coresight/devices/etm<N>/nr_ss_cmp 73 Date: April 2015 74 KernelVersion: 4.01 75 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 76 Description: (Read) Indicates the number of single-shot comparator controls that 77 are available for tracing. 78 79 What: /sys/bus/coresight/devices/etm<N>/reset 80 Date: April 2015 81 KernelVersion: 4.01 82 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 83 Description: (Write) Cancels all configuration on a trace unit and set it back 84 to its boot configuration. 85 86 What: /sys/bus/coresight/devices/etm<N>/mode 87 Date: April 2015 88 KernelVersion: 4.01 89 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 90 Description: (RW) Controls various modes supported by this ETM, for example 91 P0 instruction tracing, branch broadcast, cycle counting and 92 context ID tracing. 93 94 What: /sys/bus/coresight/devices/etm<N>/pe 95 Date: April 2015 96 KernelVersion: 4.01 97 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 98 Description: (RW) Controls which PE to trace. 99 100 What: /sys/bus/coresight/devices/etm<N>/event 101 Date: April 2015 102 KernelVersion: 4.01 103 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 104 Description: (RW) Controls the tracing of arbitrary events from bank 0 to 3. 105 106 What: /sys/bus/coresight/devices/etm<N>/event_instren 107 Date: April 2015 108 KernelVersion: 4.01 109 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 110 Description: (RW) Controls the behavior of the events in bank 0 to 3. 111 112 What: /sys/bus/coresight/devices/etm<N>/event_ts 113 Date: April 2015 114 KernelVersion: 4.01 115 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 116 Description: (RW) Controls the insertion of global timestamps in the trace 117 streams. 118 119 What: /sys/bus/coresight/devices/etm<N>/syncfreq 120 Date: April 2015 121 KernelVersion: 4.01 122 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 123 Description: (RW) Controls how often trace synchronization requests occur. 124 125 What: /sys/bus/coresight/devices/etm<N>/cyc_threshold 126 Date: April 2015 127 KernelVersion: 4.01 128 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 129 Description: (RW) Sets the threshold value for cycle counting. 130 131 What: /sys/bus/coresight/devices/etm<N>/bb_ctrl 132 Date: April 2015 133 KernelVersion: 4.01 134 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 135 Description: (RW) Controls which regions in the memory map are enabled to 136 use branch broadcasting. 137 138 What: /sys/bus/coresight/devices/etm<N>/event_vinst 139 Date: April 2015 140 KernelVersion: 4.01 141 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 142 Description: (RW) Controls instruction trace filtering. 143 144 What: /sys/bus/coresight/devices/etm<N>/s_exlevel_vinst 145 Date: April 2015 146 KernelVersion: 4.01 147 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 148 Description: (RW) In Secure state, each bit controls whether instruction 149 tracing is enabled for the corresponding exception level. 150 151 What: /sys/bus/coresight/devices/etm<N>/ns_exlevel_vinst 152 Date: April 2015 153 KernelVersion: 4.01 154 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 155 Description: (RW) In non-secure state, each bit controls whether instruction 156 tracing is enabled for the corresponding exception level. 157 158 What: /sys/bus/coresight/devices/etm<N>/addr_idx 159 Date: April 2015 160 KernelVersion: 4.01 161 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 162 Description: (RW) Select which address comparator or pair (of comparators) to 163 work with. 164 165 What: /sys/bus/coresight/devices/etm<N>/addr_instdatatype 166 Date: April 2015 167 KernelVersion: 4.01 168 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 169 Description: (RW) Controls what type of comparison the trace unit performs. 170 171 What: /sys/bus/coresight/devices/etm<N>/addr_single 172 Date: April 2015 173 KernelVersion: 4.01 174 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 175 Description: (RW) Used to setup single address comparator values. 176 177 What: /sys/bus/coresight/devices/etm<N>/addr_range 178 Date: April 2015 179 KernelVersion: 4.01 180 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 181 Description: (RW) Used to setup address range comparator values. 182 183 What: /sys/bus/coresight/devices/etm<N>/seq_idx 184 Date: April 2015 185 KernelVersion: 4.01 186 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 187 Description: (RW) Select which sequensor. 188 189 What: /sys/bus/coresight/devices/etm<N>/seq_state 190 Date: April 2015 191 KernelVersion: 4.01 192 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 193 Description: (RW) Use this to set, or read, the sequencer state. 194 195 What: /sys/bus/coresight/devices/etm<N>/seq_event 196 Date: April 2015 197 KernelVersion: 4.01 198 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 199 Description: (RW) Moves the sequencer state to a specific state. 200 201 What: /sys/bus/coresight/devices/etm<N>/seq_reset_event 202 Date: April 2015 203 KernelVersion: 4.01 204 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 205 Description: (RW) Moves the sequencer to state 0 when a programmed event 206 occurs. 207 208 What: /sys/bus/coresight/devices/etm<N>/cntr_idx 209 Date: April 2015 210 KernelVersion: 4.01 211 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 212 Description: (RW) Select which counter unit to work with. 213 214 What: /sys/bus/coresight/devices/etm<N>/cntrldvr 215 Date: April 2015 216 KernelVersion: 4.01 217 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 218 Description: (RW) This sets or returns the reload count value of the 219 specific counter. 220 221 What: /sys/bus/coresight/devices/etm<N>/cntr_val 222 Date: April 2015 223 KernelVersion: 4.01 224 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 225 Description: (RW) This sets or returns the current count value of the 226 specific counter. 227 228 What: /sys/bus/coresight/devices/etm<N>/cntr_ctrl 229 Date: April 2015 230 KernelVersion: 4.01 231 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 232 Description: (RW) Controls the operation of the selected counter. 233 234 What: /sys/bus/coresight/devices/etm<N>/res_idx 235 Date: April 2015 236 KernelVersion: 4.01 237 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 238 Description: (RW) Select which resource selection unit to work with. 239 240 What: /sys/bus/coresight/devices/etm<N>/res_ctrl 241 Date: April 2015 242 KernelVersion: 4.01 243 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 244 Description: (RW) Controls the selection of the resources in the trace unit. 245 246 What: /sys/bus/coresight/devices/etm<N>/ctxid_idx 247 Date: April 2015 248 KernelVersion: 4.01 249 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 250 Description: (RW) Select which context ID comparator to work with. 251 252 What: /sys/bus/coresight/devices/etm<N>/ctxid_pid 253 Date: April 2015 254 KernelVersion: 4.01 255 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 256 Description: (RW) Get/Set the context ID comparator value to trigger on. 257 258 What: /sys/bus/coresight/devices/etm<N>/ctxid_masks 259 Date: April 2015 260 KernelVersion: 4.01 261 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 262 Description: (RW) Mask for all 8 context ID comparator value 263 registers (if implemented). 264 265 What: /sys/bus/coresight/devices/etm<N>/vmid_idx 266 Date: April 2015 267 KernelVersion: 4.01 268 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 269 Description: (RW) Select which virtual machine ID comparator to work with. 270 271 What: /sys/bus/coresight/devices/etm<N>/vmid_val 272 Date: April 2015 273 KernelVersion: 4.01 274 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 275 Description: (RW) Get/Set the virtual machine ID comparator value to 276 trigger on. 277 278 What: /sys/bus/coresight/devices/etm<N>/vmid_masks 279 Date: April 2015 280 KernelVersion: 4.01 281 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 282 Description: (RW) Mask for all 8 virtual machine ID comparator value 283 registers (if implemented). 284 285 What: /sys/bus/coresight/devices/etm<N>/addr_exlevel_s_ns 286 Date: December 2019 287 KernelVersion: 5.5 288 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 289 Description: (RW) Set the Exception Level matching bits for secure and 290 non-secure exception levels. 291 292 What: /sys/bus/coresight/devices/etm<N>/vinst_pe_cmp_start_stop 293 Date: December 2019 294 KernelVersion: 5.5 295 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 296 Description: (RW) Access the start stop control register for PE input 297 comparators. 298 299 What: /sys/bus/coresight/devices/etm<N>/addr_cmp_view 300 Date: December 2019 301 KernelVersion: 5.5 302 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 303 Description: (Read) Print the current settings for the selected address 304 comparator. 305 306 What: /sys/bus/coresight/devices/etm<N>/sshot_idx 307 Date: December 2019 308 KernelVersion: 5.5 309 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 310 Description: (RW) Select the single shot control register to access. 311 312 What: /sys/bus/coresight/devices/etm<N>/sshot_ctrl 313 Date: December 2019 314 KernelVersion: 5.5 315 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 316 Description: (RW) Access the selected single shot control register. 317 318 What: /sys/bus/coresight/devices/etm<N>/sshot_status 319 Date: December 2019 320 KernelVersion: 5.5 321 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 322 Description: (Read) Print the current value of the selected single shot 323 status register. 324 325 What: /sys/bus/coresight/devices/etm<N>/sshot_pe_ctrl 326 Date: December 2019 327 KernelVersion: 5.5 328 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 329 Description: (RW) Access the selected single show PE comparator control 330 register. 331 332 What: /sys/bus/coresight/devices/etm<N>/mgmt/trcoslsr 333 Date: April 2015 334 KernelVersion: 4.01 335 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 336 Description: (Read) Print the content of the OS Lock Status Register (0x304). 337 The value it taken directly from the HW. 338 339 What: /sys/bus/coresight/devices/etm<N>/mgmt/trcpdcr 340 Date: April 2015 341 KernelVersion: 4.01 342 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 343 Description: (Read) Print the content of the Power Down Control Register 344 (0x310). The value is taken directly from the HW. 345 346 What: /sys/bus/coresight/devices/etm<N>/mgmt/trcpdsr 347 Date: April 2015 348 KernelVersion: 4.01 349 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 350 Description: (Read) Print the content of the Power Down Status Register 351 (0x314). The value is taken directly from the HW. 352 353 What: /sys/bus/coresight/devices/etm<N>/mgmt/trclsr 354 Date: April 2015 355 KernelVersion: 4.01 356 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 357 Description: (Read) Print the content of the SW Lock Status Register 358 (0xFB4). The value is taken directly from the HW. 359 360 What: /sys/bus/coresight/devices/etm<N>/mgmt/trcauthstatus 361 Date: April 2015 362 KernelVersion: 4.01 363 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 364 Description: (Read) Print the content of the Authentication Status Register 365 (0xFB8). The value is taken directly from the HW. 366 367 What: /sys/bus/coresight/devices/etm<N>/mgmt/trcdevid 368 Date: April 2015 369 KernelVersion: 4.01 370 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 371 Description: (Read) Print the content of the Device ID Register 372 (0xFC8). The value is taken directly from the HW. 373 374 What: /sys/bus/coresight/devices/etm<N>/mgmt/trcdevarch 375 Date: January 2021 376 KernelVersion: 5.12 377 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 378 Description: (Read) Print the content of the Device Architecture Register 379 (offset 0xFBC). The value is taken directly read 380 from the HW. 381 382 What: /sys/bus/coresight/devices/etm<N>/mgmt/trcdevtype 383 Date: April 2015 384 KernelVersion: 4.01 385 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 386 Description: (Read) Print the content of the Device Type Register 387 (0xFCC). The value is taken directly from the HW. 388 389 What: /sys/bus/coresight/devices/etm<N>/mgmt/trcpidr0 390 Date: April 2015 391 KernelVersion: 4.01 392 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 393 Description: (Read) Print the content of the Peripheral ID0 Register 394 (0xFE0). The value is taken directly from the HW. 395 396 What: /sys/bus/coresight/devices/etm<N>/mgmt/trcpidr1 397 Date: April 2015 398 KernelVersion: 4.01 399 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 400 Description: (Read) Print the content of the Peripheral ID1 Register 401 (0xFE4). The value is taken directly from the HW. 402 403 What: /sys/bus/coresight/devices/etm<N>/mgmt/trcpidr2 404 Date: April 2015 405 KernelVersion: 4.01 406 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 407 Description: (Read) Print the content of the Peripheral ID2 Register 408 (0xFE8). The value is taken directly from the HW. 409 410 What: /sys/bus/coresight/devices/etm<N>/mgmt/trcpidr3 411 Date: April 2015 412 KernelVersion: 4.01 413 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 414 Description: (Read) Print the content of the Peripheral ID3 Register 415 (0xFEC). The value is taken directly from the HW. 416 417 What: /sys/bus/coresight/devices/etm<N>/mgmt/trcconfig 418 Date: February 2016 419 KernelVersion: 4.07 420 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 421 Description: (Read) Print the content of the trace configuration register 422 (0x010) as currently set by SW. 423 424 What: /sys/bus/coresight/devices/etm<N>/mgmt/trctraceid 425 Date: February 2016 426 KernelVersion: 4.07 427 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 428 Description: (Read) Print the content of the trace ID register (0x040). 429 430 What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr0 431 Date: April 2015 432 KernelVersion: 4.01 433 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 434 Description: (Read) Returns the tracing capabilities of the trace unit (0x1E0). 435 The value is taken directly from the HW. 436 437 What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr1 438 Date: April 2015 439 KernelVersion: 4.01 440 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 441 Description: (Read) Returns the tracing capabilities of the trace unit (0x1E4). 442 The value is taken directly from the HW. 443 444 What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr2 445 Date: April 2015 446 KernelVersion: 4.01 447 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 448 Description: (Read) Returns the maximum size of the data value, data address, 449 VMID, context ID and instruction address in the trace unit 450 (0x1E8). The value is taken directly from the HW. 451 452 What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr3 453 Date: April 2015 454 KernelVersion: 4.01 455 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 456 Description: (Read) Returns the value associated with various resources 457 available to the trace unit. See the Trace Macrocell 458 architecture specification for more details (0x1E8). 459 The value is taken directly from the HW. 460 461 What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr4 462 Date: April 2015 463 KernelVersion: 4.01 464 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 465 Description: (Read) Returns how many resources the trace unit supports (0x1F0). 466 The value is taken directly from the HW. 467 468 What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr5 469 Date: April 2015 470 KernelVersion: 4.01 471 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 472 Description: (Read) Returns how many resources the trace unit supports (0x1F4). 473 The value is taken directly from the HW. 474 475 What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr8 476 Date: April 2015 477 KernelVersion: 4.01 478 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 479 Description: (Read) Returns the maximum speculation depth of the instruction 480 trace stream. (0x180). The value is taken directly from the HW. 481 482 What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr9 483 Date: April 2015 484 KernelVersion: 4.01 485 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 486 Description: (Read) Returns the number of P0 right-hand keys that the trace unit 487 can use (0x184). The value is taken directly from the HW. 488 489 What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr10 490 Date: April 2015 491 KernelVersion: 4.01 492 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 493 Description: (Read) Returns the number of P1 right-hand keys that the trace unit 494 can use (0x188). The value is taken directly from the HW. 495 496 What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr11 497 Date: April 2015 498 KernelVersion: 4.01 499 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 500 Description: (Read) Returns the number of special P1 right-hand keys that the 501 trace unit can use (0x18C). The value is taken directly from 502 the HW. 503 504 What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr12 505 Date: April 2015 506 KernelVersion: 4.01 507 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 508 Description: (Read) Returns the number of conditional P1 right-hand keys that 509 the trace unit can use (0x190). The value is taken directly 510 from the HW. 511 512 What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr13 513 Date: April 2015 514 KernelVersion: 4.01 515 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 516 Description: (Read) Returns the number of special conditional P1 right-hand keys 517 that the trace unit can use (0x194). The value is taken 518 directly from the HW. 519 520 What: /sys/bus/coresight/devices/etm<N>/ts_source 521 Date: October 2022 522 KernelVersion: 6.1 523 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> or Suzuki K Poulose <suzuki.poulose@arm.com> 524 Description: (Read) When FEAT_TRF is implemented, value of TRFCR_ELx.TS used for 525 trace session. Otherwise -1 indicates an unknown time source. Check 526 trcidr0.tssize to see if a global timestamp is available.
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