1 .. SPDX-License-Identifier: GPL-2.0 2 3 ================= 4 PCI Test Function 5 ================= 6 7 :Author: Kishon Vijay Abraham I <kishon@ti.com> 8 9 Traditionally PCI RC has always been validated by using standard 10 PCI cards like ethernet PCI cards or USB PCI cards or SATA PCI cards. 11 However with the addition of EP-core in linux kernel, it is possible 12 to configure a PCI controller that can operate in EP mode to work as 13 a test device. 14 15 The PCI endpoint test device is a virtual device (defined in software) 16 used to test the endpoint functionality and serve as a sample driver 17 for other PCI endpoint devices (to use the EP framework). 18 19 The PCI endpoint test device has the following registers: 20 21 1) PCI_ENDPOINT_TEST_MAGIC 22 2) PCI_ENDPOINT_TEST_COMMAND 23 3) PCI_ENDPOINT_TEST_STATUS 24 4) PCI_ENDPOINT_TEST_SRC_ADDR 25 5) PCI_ENDPOINT_TEST_DST_ADDR 26 6) PCI_ENDPOINT_TEST_SIZE 27 7) PCI_ENDPOINT_TEST_CHECKSUM 28 8) PCI_ENDPOINT_TEST_IRQ_TYPE 29 9) PCI_ENDPOINT_TEST_IRQ_NUMBER 30 31 * PCI_ENDPOINT_TEST_MAGIC 32 33 This register will be used to test BAR0. A known pattern will be written 34 and read back from MAGIC register to verify BAR0. 35 36 * PCI_ENDPOINT_TEST_COMMAND 37 38 This register will be used by the host driver to indicate the function 39 that the endpoint device must perform. 40 41 ======== ================================================================ 42 Bitfield Description 43 ======== ================================================================ 44 Bit 0 raise legacy IRQ 45 Bit 1 raise MSI IRQ 46 Bit 2 raise MSI-X IRQ 47 Bit 3 read command (read data from RC buffer) 48 Bit 4 write command (write data to RC buffer) 49 Bit 5 copy command (copy data from one RC buffer to another RC buffer) 50 ======== ================================================================ 51 52 * PCI_ENDPOINT_TEST_STATUS 53 54 This register reflects the status of the PCI endpoint device. 55 56 ======== ============================== 57 Bitfield Description 58 ======== ============================== 59 Bit 0 read success 60 Bit 1 read fail 61 Bit 2 write success 62 Bit 3 write fail 63 Bit 4 copy success 64 Bit 5 copy fail 65 Bit 6 IRQ raised 66 Bit 7 source address is invalid 67 Bit 8 destination address is invalid 68 ======== ============================== 69 70 * PCI_ENDPOINT_TEST_SRC_ADDR 71 72 This register contains the source address (RC buffer address) for the 73 COPY/READ command. 74 75 * PCI_ENDPOINT_TEST_DST_ADDR 76 77 This register contains the destination address (RC buffer address) for 78 the COPY/WRITE command. 79 80 * PCI_ENDPOINT_TEST_IRQ_TYPE 81 82 This register contains the interrupt type (Legacy/MSI) triggered 83 for the READ/WRITE/COPY and raise IRQ (Legacy/MSI) commands. 84 85 Possible types: 86 87 ====== == 88 Legacy 0 89 MSI 1 90 MSI-X 2 91 ====== == 92 93 * PCI_ENDPOINT_TEST_IRQ_NUMBER 94 95 This register contains the triggered ID interrupt. 96 97 Admissible values: 98 99 ====== =========== 100 Legacy 0 101 MSI [1 .. 32] 102 MSI-X [1 .. 2048] 103 ====== ===========
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.