1 ===========================
2 ARM64 CPU Feature Registers
3 ===========================
4
5 Author: Suzuki K Poulose <suzuki.poulose@arm.com>
6
7
8 This file describes the ABI for exporting the AArch64 CPU ID/feature
9 registers to userspace. The availability of this ABI is advertised
10 via the HWCAP_CPUID in HWCAPs.
11
12 1. Motivation
13 -------------
14
15 The ARM architecture defines a set of feature registers, which describe
16 the capabilities of the CPU/system. Access to these system registers is
17 restricted from EL0 and there is no reliable way for an application to
18 extract this information to make better decisions at runtime. There is
19 limited information available to the application via HWCAPs, however
20 there are some issues with their usage.
21
22 a) Any change to the HWCAPs requires an update to userspace (e.g libc)
23 to detect the new changes, which can take a long time to appear in
24 distributions. Exposing the registers allows applications to get the
25 information without requiring updates to the toolchains.
26
27 b) Access to HWCAPs is sometimes limited (e.g prior to libc, or
28 when ld is initialised at startup time).
29
30 c) HWCAPs cannot represent non-boolean information effectively. The
31 architecture defines a canonical format for representing features
32 in the ID registers; this is well defined and is capable of
33 representing all valid architecture variations.
34
35
36 2. Requirements
37 ---------------
38
39 a) Safety:
40
41 Applications should be able to use the information provided by the
42 infrastructure to run safely across the system. This has greater
43 implications on a system with heterogeneous CPUs.
44 The infrastructure exports a value that is safe across all the
45 available CPU on the system.
46
47 e.g, If at least one CPU doesn't implement CRC32 instructions, while
48 others do, we should report that the CRC32 is not implemented.
49 Otherwise an application could crash when scheduled on the CPU
50 which doesn't support CRC32.
51
52 b) Security:
53
54 Applications should only be able to receive information that is
55 relevant to the normal operation in userspace. Hence, some of the
56 fields are masked out(i.e, made invisible) and their values are set to
57 indicate the feature is 'not supported'. See Section 4 for the list
58 of visible features. Also, the kernel may manipulate the fields
59 based on what it supports. e.g, If FP is not supported by the
60 kernel, the values could indicate that the FP is not available
61 (even when the CPU provides it).
62
63 c) Implementation Defined Features
64
65 The infrastructure doesn't expose any register which is
66 IMPLEMENTATION DEFINED as per ARMv8-A Architecture.
67
68 d) CPU Identification:
69
70 MIDR_EL1 is exposed to help identify the processor. On a
71 heterogeneous system, this could be racy (just like getcpu()). The
72 process could be migrated to another CPU by the time it uses the
73 register value, unless the CPU affinity is set. Hence, there is no
74 guarantee that the value reflects the processor that it is
75 currently executing on. The REVIDR is not exposed due to this
76 constraint, as REVIDR makes sense only in conjunction with the
77 MIDR. Alternately, MIDR_EL1 and REVIDR_EL1 are exposed via sysfs
78 at::
79
80 /sys/devices/system/cpu/cpu$ID/regs/identification/
81 \- midr
82 \- revidr
83
84 3. Implementation
85 --------------------
86
87 The infrastructure is built on the emulation of the 'MRS' instruction.
88 Accessing a restricted system register from an application generates an
89 exception and ends up in SIGILL being delivered to the process.
90 The infrastructure hooks into the exception handler and emulates the
91 operation if the source belongs to the supported system register space.
92
93 The infrastructure emulates only the following system register space::
94
95 Op0=3, Op1=0, CRn=0, CRm=0,2,3,4,5,6,7
96
97 (See Table C5-6 'System instruction encodings for non-Debug System
98 register accesses' in ARMv8 ARM DDI 0487A.h, for the list of
99 registers).
100
101 The following rules are applied to the value returned by the
102 infrastructure:
103
104 a) The value of an 'IMPLEMENTATION DEFINED' field is set to 0.
105 b) The value of a reserved field is populated with the reserved
106 value as defined by the architecture.
107 c) The value of a 'visible' field holds the system wide safe value
108 for the particular feature (except for MIDR_EL1, see section 4).
109 d) All other fields (i.e, invisible fields) are set to indicate
110 the feature is missing (as defined by the architecture).
111
112 4. List of registers with visible features
113 -------------------------------------------
114
115 1) ID_AA64ISAR0_EL1 - Instruction Set Attribute Register 0
116
117 +------------------------------+---------+---------+
118 | Name | bits | visible |
119 +------------------------------+---------+---------+
120 | RNDR | [63-60] | y |
121 +------------------------------+---------+---------+
122 | TS | [55-52] | y |
123 +------------------------------+---------+---------+
124 | FHM | [51-48] | y |
125 +------------------------------+---------+---------+
126 | DP | [47-44] | y |
127 +------------------------------+---------+---------+
128 | SM4 | [43-40] | y |
129 +------------------------------+---------+---------+
130 | SM3 | [39-36] | y |
131 +------------------------------+---------+---------+
132 | SHA3 | [35-32] | y |
133 +------------------------------+---------+---------+
134 | RDM | [31-28] | y |
135 +------------------------------+---------+---------+
136 | ATOMICS | [23-20] | y |
137 +------------------------------+---------+---------+
138 | CRC32 | [19-16] | y |
139 +------------------------------+---------+---------+
140 | SHA2 | [15-12] | y |
141 +------------------------------+---------+---------+
142 | SHA1 | [11-8] | y |
143 +------------------------------+---------+---------+
144 | AES | [7-4] | y |
145 +------------------------------+---------+---------+
146
147
148 2) ID_AA64PFR0_EL1 - Processor Feature Register 0
149
150 +------------------------------+---------+---------+
151 | Name | bits | visible |
152 +------------------------------+---------+---------+
153 | DIT | [51-48] | y |
154 +------------------------------+---------+---------+
155 | SVE | [35-32] | y |
156 +------------------------------+---------+---------+
157 | GIC | [27-24] | n |
158 +------------------------------+---------+---------+
159 | AdvSIMD | [23-20] | y |
160 +------------------------------+---------+---------+
161 | FP | [19-16] | y |
162 +------------------------------+---------+---------+
163 | EL3 | [15-12] | n |
164 +------------------------------+---------+---------+
165 | EL2 | [11-8] | n |
166 +------------------------------+---------+---------+
167 | EL1 | [7-4] | n |
168 +------------------------------+---------+---------+
169 | EL0 | [3-0] | n |
170 +------------------------------+---------+---------+
171
172
173 3) ID_AA64PFR1_EL1 - Processor Feature Register 1
174
175 +------------------------------+---------+---------+
176 | Name | bits | visible |
177 +------------------------------+---------+---------+
178 | SME | [27-24] | y |
179 +------------------------------+---------+---------+
180 | MTE | [11-8] | y |
181 +------------------------------+---------+---------+
182 | SSBS | [7-4] | y |
183 +------------------------------+---------+---------+
184 | BT | [3-0] | y |
185 +------------------------------+---------+---------+
186
187
188 4) MIDR_EL1 - Main ID Register
189
190 +------------------------------+---------+---------+
191 | Name | bits | visible |
192 +------------------------------+---------+---------+
193 | Implementer | [31-24] | y |
194 +------------------------------+---------+---------+
195 | Variant | [23-20] | y |
196 +------------------------------+---------+---------+
197 | Architecture | [19-16] | y |
198 +------------------------------+---------+---------+
199 | PartNum | [15-4] | y |
200 +------------------------------+---------+---------+
201 | Revision | [3-0] | y |
202 +------------------------------+---------+---------+
203
204 NOTE: The 'visible' fields of MIDR_EL1 will contain the value
205 as available on the CPU where it is fetched and is not a system
206 wide safe value.
207
208 5) ID_AA64ISAR1_EL1 - Instruction set attribute register 1
209
210 +------------------------------+---------+---------+
211 | Name | bits | visible |
212 +------------------------------+---------+---------+
213 | I8MM | [55-52] | y |
214 +------------------------------+---------+---------+
215 | DGH | [51-48] | y |
216 +------------------------------+---------+---------+
217 | BF16 | [47-44] | y |
218 +------------------------------+---------+---------+
219 | SB | [39-36] | y |
220 +------------------------------+---------+---------+
221 | FRINTTS | [35-32] | y |
222 +------------------------------+---------+---------+
223 | GPI | [31-28] | y |
224 +------------------------------+---------+---------+
225 | GPA | [27-24] | y |
226 +------------------------------+---------+---------+
227 | LRCPC | [23-20] | y |
228 +------------------------------+---------+---------+
229 | FCMA | [19-16] | y |
230 +------------------------------+---------+---------+
231 | JSCVT | [15-12] | y |
232 +------------------------------+---------+---------+
233 | API | [11-8] | y |
234 +------------------------------+---------+---------+
235 | APA | [7-4] | y |
236 +------------------------------+---------+---------+
237 | DPB | [3-0] | y |
238 +------------------------------+---------+---------+
239
240 6) ID_AA64MMFR0_EL1 - Memory model feature register 0
241
242 +------------------------------+---------+---------+
243 | Name | bits | visible |
244 +------------------------------+---------+---------+
245 | ECV | [63-60] | y |
246 +------------------------------+---------+---------+
247
248 7) ID_AA64MMFR2_EL1 - Memory model feature register 2
249
250 +------------------------------+---------+---------+
251 | Name | bits | visible |
252 +------------------------------+---------+---------+
253 | AT | [35-32] | y |
254 +------------------------------+---------+---------+
255
256 8) ID_AA64ZFR0_EL1 - SVE feature ID register 0
257
258 +------------------------------+---------+---------+
259 | Name | bits | visible |
260 +------------------------------+---------+---------+
261 | F64MM | [59-56] | y |
262 +------------------------------+---------+---------+
263 | F32MM | [55-52] | y |
264 +------------------------------+---------+---------+
265 | I8MM | [47-44] | y |
266 +------------------------------+---------+---------+
267 | SM4 | [43-40] | y |
268 +------------------------------+---------+---------+
269 | SHA3 | [35-32] | y |
270 +------------------------------+---------+---------+
271 | B16B16 | [27-24] | y |
272 +------------------------------+---------+---------+
273 | BF16 | [23-20] | y |
274 +------------------------------+---------+---------+
275 | BitPerm | [19-16] | y |
276 +------------------------------+---------+---------+
277 | AES | [7-4] | y |
278 +------------------------------+---------+---------+
279 | SVEVer | [3-0] | y |
280 +------------------------------+---------+---------+
281
282 8) ID_AA64MMFR1_EL1 - Memory model feature register 1
283
284 +------------------------------+---------+---------+
285 | Name | bits | visible |
286 +------------------------------+---------+---------+
287 | AFP | [47-44] | y |
288 +------------------------------+---------+---------+
289
290 9) ID_AA64ISAR2_EL1 - Instruction set attribute register 2
291
292 +------------------------------+---------+---------+
293 | Name | bits | visible |
294 +------------------------------+---------+---------+
295 | CSSC | [55-52] | y |
296 +------------------------------+---------+---------+
297 | RPRFM | [51-48] | y |
298 +------------------------------+---------+---------+
299 | BC | [23-20] | y |
300 +------------------------------+---------+---------+
301 | MOPS | [19-16] | y |
302 +------------------------------+---------+---------+
303 | APA3 | [15-12] | y |
304 +------------------------------+---------+---------+
305 | GPA3 | [11-8] | y |
306 +------------------------------+---------+---------+
307 | RPRES | [7-4] | y |
308 +------------------------------+---------+---------+
309 | WFXT | [3-0] | y |
310 +------------------------------+---------+---------+
311
312 10) MVFR0_EL1 - AArch32 Media and VFP Feature Register 0
313
314 +------------------------------+---------+---------+
315 | Name | bits | visible |
316 +------------------------------+---------+---------+
317 | FPDP | [11-8] | y |
318 +------------------------------+---------+---------+
319
320 11) MVFR1_EL1 - AArch32 Media and VFP Feature Register 1
321
322 +------------------------------+---------+---------+
323 | Name | bits | visible |
324 +------------------------------+---------+---------+
325 | SIMDFMAC | [31-28] | y |
326 +------------------------------+---------+---------+
327 | SIMDSP | [19-16] | y |
328 +------------------------------+---------+---------+
329 | SIMDInt | [15-12] | y |
330 +------------------------------+---------+---------+
331 | SIMDLS | [11-8] | y |
332 +------------------------------+---------+---------+
333
334 12) ID_ISAR5_EL1 - AArch32 Instruction Set Attribute Register 5
335
336 +------------------------------+---------+---------+
337 | Name | bits | visible |
338 +------------------------------+---------+---------+
339 | CRC32 | [19-16] | y |
340 +------------------------------+---------+---------+
341 | SHA2 | [15-12] | y |
342 +------------------------------+---------+---------+
343 | SHA1 | [11-8] | y |
344 +------------------------------+---------+---------+
345 | AES | [7-4] | y |
346 +------------------------------+---------+---------+
347
348
349 Appendix I: Example
350 -------------------
351
352 ::
353
354 /*
355 * Sample program to demonstrate the MRS emulation ABI.
356 *
357 * Copyright (C) 2015-2016, ARM Ltd
358 *
359 * Author: Suzuki K Poulose <suzuki.poulose@arm.com>
360 *
361 * This program is free software; you can redistribute it and/or modify
362 * it under the terms of the GNU General Public License version 2 as
363 * published by the Free Software Foundation.
364 *
365 * This program is distributed in the hope that it will be useful,
366 * but WITHOUT ANY WARRANTY; without even the implied warranty of
367 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
368 * GNU General Public License for more details.
369 * This program is free software; you can redistribute it and/or modify
370 * it under the terms of the GNU General Public License version 2 as
371 * published by the Free Software Foundation.
372 *
373 * This program is distributed in the hope that it will be useful,
374 * but WITHOUT ANY WARRANTY; without even the implied warranty of
375 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
376 * GNU General Public License for more details.
377 */
378
379 #include <asm/hwcap.h>
380 #include <stdio.h>
381 #include <sys/auxv.h>
382
383 #define get_cpu_ftr(id) ({ \
384 unsigned long __val; \
385 asm("mrs %0, "#id : "=r" (__val)); \
386 printf("%-20s: 0x%016lx\n", #id, __val); \
387 })
388
389 int main(void)
390 {
391
392 if (!(getauxval(AT_HWCAP) & HWCAP_CPUID)) {
393 fputs("CPUID registers unavailable\n", stderr);
394 return 1;
395 }
396
397 get_cpu_ftr(ID_AA64ISAR0_EL1);
398 get_cpu_ftr(ID_AA64ISAR1_EL1);
399 get_cpu_ftr(ID_AA64MMFR0_EL1);
400 get_cpu_ftr(ID_AA64MMFR1_EL1);
401 get_cpu_ftr(ID_AA64PFR0_EL1);
402 get_cpu_ftr(ID_AA64PFR1_EL1);
403 get_cpu_ftr(ID_AA64DFR0_EL1);
404 get_cpu_ftr(ID_AA64DFR1_EL1);
405
406 get_cpu_ftr(MIDR_EL1);
407 get_cpu_ftr(MPIDR_EL1);
408 get_cpu_ftr(REVIDR_EL1);
409
410 #if 0
411 /* Unexposed register access causes SIGILL */
412 get_cpu_ftr(ID_MMFR0_EL1);
413 #endif
414
415 return 0;
416 }
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