1 .. SPDX-License-Identifier: GPL-2.0 2 3 ======================================= 4 IRQ chip model (hierarchy) of LoongArch 5 ======================================= 6 7 Currently, LoongArch based processors (e.g. Loongson-3A5000) can only work together 8 with LS7A chipsets. The irq chips in LoongArch computers include CPUINTC (CPU Core 9 Interrupt Controller), LIOINTC (Legacy I/O Interrupt Controller), EIOINTC (Extended 10 I/O Interrupt Controller), HTVECINTC (Hyper-Transport Vector Interrupt Controller), 11 PCH-PIC (Main Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller 12 in LS7A chipset) and PCH-MSI (MSI Interrupt Controller). 13 14 CPUINTC is a per-core controller (in CPU), LIOINTC/EIOINTC/HTVECINTC are per-package 15 controllers (in CPU), while PCH-PIC/PCH-LPC/PCH-MSI are controllers out of CPU (i.e., 16 in chipsets). These controllers (in other words, irqchips) are linked in a hierarchy, 17 and there are two models of hierarchy (legacy model and extended model). 18 19 Legacy IRQ model 20 ================ 21 22 In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go 23 to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices 24 interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by HTVECINTC, and then go 25 to LIOINTC, and then CPUINTC:: 26 27 +-----+ +---------+ +-------+ 28 | IPI | --> | CPUINTC | <-- | Timer | 29 +-----+ +---------+ +-------+ 30 ^ 31 | 32 +---------+ +-------+ 33 | LIOINTC | <-- | UARTs | 34 +---------+ +-------+ 35 ^ 36 | 37 +-----------+ 38 | HTVECINTC | 39 +-----------+ 40 ^ ^ 41 | | 42 +---------+ +---------+ 43 | PCH-PIC | | PCH-MSI | 44 +---------+ +---------+ 45 ^ ^ ^ 46 | | | 47 +---------+ +---------+ +---------+ 48 | PCH-LPC | | Devices | | Devices | 49 +---------+ +---------+ +---------+ 50 ^ 51 | 52 +---------+ 53 | Devices | 54 +---------+ 55 56 Extended IRQ model 57 ================== 58 59 In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go 60 to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices 61 interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by EIOINTC, and then go to 62 to CPUINTC directly:: 63 64 +-----+ +---------+ +-------+ 65 | IPI | --> | CPUINTC | <-- | Timer | 66 +-----+ +---------+ +-------+ 67 ^ ^ 68 | | 69 +---------+ +---------+ +-------+ 70 | EIOINTC | | LIOINTC | <-- | UARTs | 71 +---------+ +---------+ +-------+ 72 ^ ^ 73 | | 74 +---------+ +---------+ 75 | PCH-PIC | | PCH-MSI | 76 +---------+ +---------+ 77 ^ ^ ^ 78 | | | 79 +---------+ +---------+ +---------+ 80 | PCH-LPC | | Devices | | Devices | 81 +---------+ +---------+ +---------+ 82 ^ 83 | 84 +---------+ 85 | Devices | 86 +---------+ 87 88 Advanced Extended IRQ model 89 =========================== 90 91 In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go 92 to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, PCH-MSI interrupts go 93 to AVECINTC, and then go to CPUINTC directly, while all other devices interrupts 94 go to PCH-PIC/PCH-LPC and gathered by EIOINTC, and then go to CPUINTC directly:: 95 96 +-----+ +-----------------------+ +-------+ 97 | IPI | --> | CPUINTC | <-- | Timer | 98 +-----+ +-----------------------+ +-------+ 99 ^ ^ ^ 100 | | | 101 +---------+ +----------+ +---------+ +-------+ 102 | EIOINTC | | AVECINTC | | LIOINTC | <-- | UARTs | 103 +---------+ +----------+ +---------+ +-------+ 104 ^ ^ 105 | | 106 +---------+ +---------+ 107 | PCH-PIC | | PCH-MSI | 108 +---------+ +---------+ 109 ^ ^ ^ 110 | | | 111 +---------+ +---------+ +---------+ 112 | Devices | | PCH-LPC | | Devices | 113 +---------+ +---------+ +---------+ 114 ^ 115 | 116 +---------+ 117 | Devices | 118 +---------+ 119 120 ACPI-related definitions 121 ======================== 122 123 CPUINTC:: 124 125 ACPI_MADT_TYPE_CORE_PIC; 126 struct acpi_madt_core_pic; 127 enum acpi_madt_core_pic_version; 128 129 LIOINTC:: 130 131 ACPI_MADT_TYPE_LIO_PIC; 132 struct acpi_madt_lio_pic; 133 enum acpi_madt_lio_pic_version; 134 135 EIOINTC:: 136 137 ACPI_MADT_TYPE_EIO_PIC; 138 struct acpi_madt_eio_pic; 139 enum acpi_madt_eio_pic_version; 140 141 HTVECINTC:: 142 143 ACPI_MADT_TYPE_HT_PIC; 144 struct acpi_madt_ht_pic; 145 enum acpi_madt_ht_pic_version; 146 147 PCH-PIC:: 148 149 ACPI_MADT_TYPE_BIO_PIC; 150 struct acpi_madt_bio_pic; 151 enum acpi_madt_bio_pic_version; 152 153 PCH-MSI:: 154 155 ACPI_MADT_TYPE_MSI_PIC; 156 struct acpi_madt_msi_pic; 157 enum acpi_madt_msi_pic_version; 158 159 PCH-LPC:: 160 161 ACPI_MADT_TYPE_LPC_PIC; 162 struct acpi_madt_lpc_pic; 163 enum acpi_madt_lpc_pic_version; 164 165 References 166 ========== 167 168 Documentation of Loongson-3A5000: 169 170 https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-3A5000-usermanual-1.02-CN.pdf (in Chinese) 171 172 https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-3A5000-usermanual-1.02-EN.pdf (in English) 173 174 Documentation of Loongson's LS7A chipset: 175 176 https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-usermanual-2.00-CN.pdf (in Chinese) 177 178 https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-usermanual-2.00-EN.pdf (in English) 179 180 .. Note:: 181 - CPUINTC is CSR.ECFG/CSR.ESTAT and its interrupt controller described 182 in Section 7.4 of "LoongArch Reference Manual, Vol 1"; 183 - LIOINTC is "Legacy I/OInterrupts" described in Section 11.1 of 184 "Loongson 3A5000 Processor Reference Manual"; 185 - EIOINTC is "Extended I/O Interrupts" described in Section 11.2 of 186 "Loongson 3A5000 Processor Reference Manual"; 187 - HTVECINTC is "HyperTransport Interrupts" described in Section 14.3 of 188 "Loongson 3A5000 Processor Reference Manual"; 189 - PCH-PIC/PCH-MSI is "Interrupt Controller" described in Section 5 of 190 "Loongson 7A1000 Bridge User Manual"; 191 - PCH-LPC is "LPC Interrupts" described in Section 24.3 of 192 "Loongson 7A1000 Bridge User Manual".
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