1 ================================ 2 Register Usage for Linux/PA-RISC 3 ================================ 4 5 [ an asterisk is used for planned usage which is currently unimplemented ] 6 7 General Registers as specified by ABI 8 ===================================== 9 10 Control Registers 11 ----------------- 12 13 =============================== =============================================== 14 CR 0 (Recovery Counter) used for ptrace 15 CR 1-CR 7(undefined) unused 16 CR 8 (Protection ID) per-process value* 17 CR 9, 12, 13 (PIDS) unused 18 CR10 (CCR) lazy FPU saving* 19 CR11 as specified by ABI (SAR) 20 CR14 (interruption vector) initialized to fault_vector 21 CR15 (EIEM) initialized to all ones* 22 CR16 (Interval Timer) read for cycle count/write starts Interval Tmr 23 CR17-CR22 interruption parameters 24 CR19 Interrupt Instruction Register 25 CR20 Interrupt Space Register 26 CR21 Interrupt Offset Register 27 CR22 Interrupt PSW 28 CR23 (EIRR) read for pending interrupts/write clears bits 29 CR24 (TR 0) Kernel Space Page Directory Pointer 30 CR25 (TR 1) User Space Page Directory Pointer 31 CR26 (TR 2) not used 32 CR27 (TR 3) Thread descriptor pointer 33 CR28 (TR 4) not used 34 CR29 (TR 5) not used 35 CR30 (TR 6) current / 0 36 CR31 (TR 7) Temporary register, used in various places 37 =============================== =============================================== 38 39 Space Registers (kernel mode) 40 ----------------------------- 41 42 =============================== =============================================== 43 SR0 temporary space register 44 SR4-SR7 set to 0 45 SR1 temporary space register 46 SR2 kernel should not clobber this 47 SR3 used for userspace accesses (current process) 48 =============================== =============================================== 49 50 Space Registers (user mode) 51 --------------------------- 52 53 =============================== =============================================== 54 SR0 temporary space register 55 SR1 temporary space register 56 SR2 holds space of linux gateway page 57 SR3 holds user address space value while in kernel 58 SR4-SR7 Defines short address space for user/kernel 59 =============================== =============================================== 60 61 62 Processor Status Word 63 --------------------- 64 65 =============================== =============================================== 66 W (64-bit addresses) 0 67 E (Little-endian) 0 68 S (Secure Interval Timer) 0 69 T (Taken Branch Trap) 0 70 H (Higher-privilege trap) 0 71 L (Lower-privilege trap) 0 72 N (Nullify next instruction) used by C code 73 X (Data memory break disable) 0 74 B (Taken Branch) used by C code 75 C (code address translation) 1, 0 while executing real-mode code 76 V (divide step correction) used by C code 77 M (HPMC mask) 0, 1 while executing HPMC handler* 78 C/B (carry/borrow bits) used by C code 79 O (ordered references) 1* 80 F (performance monitor) 0 81 R (Recovery Counter trap) 0 82 Q (collect interruption state) 1 (0 in code directly preceding an rfi) 83 P (Protection Identifiers) 1* 84 D (Data address translation) 1, 0 while executing real-mode code 85 I (external interrupt mask) used by cli()/sti() macros 86 =============================== =============================================== 87 88 "Invisible" Registers 89 --------------------- 90 91 =============================== =============================================== 92 PSW default W value 0 93 PSW default E value 0 94 Shadow Registers used by interruption handler code 95 TOC enable bit 1 96 =============================== =============================================== 97 98 ------------------------------------------------------------------------- 99 100 The PA-RISC architecture defines 7 registers as "shadow registers". 101 Those are used in RETURN FROM INTERRUPTION AND RESTORE instruction to reduce 102 the state save and restore time by eliminating the need for general register 103 (GR) saves and restores in interruption handlers. 104 Shadow registers are the GRs 1, 8, 9, 16, 17, 24, and 25. 105 106 ------------------------------------------------------------------------- 107 108 Register usage notes, originally from John Marvin, with some additional 109 notes from Randolph Chung. 110 111 For the general registers: 112 113 r1,r2,r19-r26,r28,r29 & r31 can be used without saving them first. And of 114 course, you need to save them if you care about them, before calling 115 another procedure. Some of the above registers do have special meanings 116 that you should be aware of: 117 118 r1: 119 The addil instruction is hardwired to place its result in r1, 120 so if you use that instruction be aware of that. 121 122 r2: 123 This is the return pointer. In general you don't want to 124 use this, since you need the pointer to get back to your 125 caller. However, it is grouped with this set of registers 126 since the caller can't rely on the value being the same 127 when you return, i.e. you can copy r2 to another register 128 and return through that register after trashing r2, and 129 that should not cause a problem for the calling routine. 130 131 r19-r22: 132 these are generally regarded as temporary registers. 133 Note that in 64 bit they are arg7-arg4. 134 135 r23-r26: 136 these are arg3-arg0, i.e. you can use them if you 137 don't care about the values that were passed in anymore. 138 139 r28,r29: 140 are ret0 and ret1. They are what you pass return values 141 in. r28 is the primary return. When returning small structures 142 r29 may also be used to pass data back to the caller. 143 144 r30: 145 stack pointer 146 147 r31: 148 the ble instruction puts the return pointer in here. 149 150 151 r3-r18,r27,r30 need to be saved and restored. r3-r18 are just 152 general purpose registers. r27 is the data pointer, and is 153 used to make references to global variables easier. r30 is 154 the stack pointer.
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