1 ============== 2 DMA attributes 3 ============== 4 5 This document describes the semantics of the DMA attributes that are 6 defined in linux/dma-mapping.h. 7 8 DMA_ATTR_WEAK_ORDERING 9 ---------------------- 10 11 DMA_ATTR_WEAK_ORDERING specifies that reads and writes to the mapping 12 may be weakly ordered, that is that reads and writes may pass each other. 13 14 Since it is optional for platforms to implement DMA_ATTR_WEAK_ORDERING, 15 those that do not will simply ignore the attribute and exhibit default 16 behavior. 17 18 DMA_ATTR_WRITE_COMBINE 19 ---------------------- 20 21 DMA_ATTR_WRITE_COMBINE specifies that writes to the mapping may be 22 buffered to improve performance. 23 24 Since it is optional for platforms to implement DMA_ATTR_WRITE_COMBINE, 25 those that do not will simply ignore the attribute and exhibit default 26 behavior. 27 28 DMA_ATTR_NO_KERNEL_MAPPING 29 -------------------------- 30 31 DMA_ATTR_NO_KERNEL_MAPPING lets the platform to avoid creating a kernel 32 virtual mapping for the allocated buffer. On some architectures creating 33 such mapping is non-trivial task and consumes very limited resources 34 (like kernel virtual address space or dma consistent address space). 35 Buffers allocated with this attribute can be only passed to user space 36 by calling dma_mmap_attrs(). By using this API, you are guaranteeing 37 that you won't dereference the pointer returned by dma_alloc_attr(). You 38 can treat it as a cookie that must be passed to dma_mmap_attrs() and 39 dma_free_attrs(). Make sure that both of these also get this attribute 40 set on each call. 41 42 Since it is optional for platforms to implement 43 DMA_ATTR_NO_KERNEL_MAPPING, those that do not will simply ignore the 44 attribute and exhibit default behavior. 45 46 DMA_ATTR_SKIP_CPU_SYNC 47 ---------------------- 48 49 By default dma_map_{single,page,sg} functions family transfer a given 50 buffer from CPU domain to device domain. Some advanced use cases might 51 require sharing a buffer between more than one device. This requires 52 having a mapping created separately for each device and is usually 53 performed by calling dma_map_{single,page,sg} function more than once 54 for the given buffer with device pointer to each device taking part in 55 the buffer sharing. The first call transfers a buffer from 'CPU' domain 56 to 'device' domain, what synchronizes CPU caches for the given region 57 (usually it means that the cache has been flushed or invalidated 58 depending on the dma direction). However, next calls to 59 dma_map_{single,page,sg}() for other devices will perform exactly the 60 same synchronization operation on the CPU cache. CPU cache synchronization 61 might be a time consuming operation, especially if the buffers are 62 large, so it is highly recommended to avoid it if possible. 63 DMA_ATTR_SKIP_CPU_SYNC allows platform code to skip synchronization of 64 the CPU cache for the given buffer assuming that it has been already 65 transferred to 'device' domain. This attribute can be also used for 66 dma_unmap_{single,page,sg} functions family to force buffer to stay in 67 device domain after releasing a mapping for it. Use this attribute with 68 care! 69 70 DMA_ATTR_FORCE_CONTIGUOUS 71 ------------------------- 72 73 By default DMA-mapping subsystem is allowed to assemble the buffer 74 allocated by dma_alloc_attrs() function from individual pages if it can 75 be mapped as contiguous chunk into device dma address space. By 76 specifying this attribute the allocated buffer is forced to be contiguous 77 also in physical memory. 78 79 DMA_ATTR_ALLOC_SINGLE_PAGES 80 --------------------------- 81 82 This is a hint to the DMA-mapping subsystem that it's probably not worth 83 the time to try to allocate memory to in a way that gives better TLB 84 efficiency (AKA it's not worth trying to build the mapping out of larger 85 pages). You might want to specify this if: 86 87 - You know that the accesses to this memory won't thrash the TLB. 88 You might know that the accesses are likely to be sequential or 89 that they aren't sequential but it's unlikely you'll ping-pong 90 between many addresses that are likely to be in different physical 91 pages. 92 - You know that the penalty of TLB misses while accessing the 93 memory will be small enough to be inconsequential. If you are 94 doing a heavy operation like decryption or decompression this 95 might be the case. 96 - You know that the DMA mapping is fairly transitory. If you expect 97 the mapping to have a short lifetime then it may be worth it to 98 optimize allocation (avoid coming up with large pages) instead of 99 getting the slight performance win of larger pages. 100 101 Setting this hint doesn't guarantee that you won't get huge pages, but it 102 means that we won't try quite as hard to get them. 103 104 .. note:: At the moment DMA_ATTR_ALLOC_SINGLE_PAGES is only implemented on ARM, 105 though ARM64 patches will likely be posted soon. 106 107 DMA_ATTR_NO_WARN 108 ---------------- 109 110 This tells the DMA-mapping subsystem to suppress allocation failure reports 111 (similarly to __GFP_NOWARN). 112 113 On some architectures allocation failures are reported with error messages 114 to the system logs. Although this can help to identify and debug problems, 115 drivers which handle failures (eg, retry later) have no problems with them, 116 and can actually flood the system logs with error messages that aren't any 117 problem at all, depending on the implementation of the retry mechanism. 118 119 So, this provides a way for drivers to avoid those error messages on calls 120 where allocation failures are not a problem, and shouldn't bother the logs. 121 122 .. note:: At the moment DMA_ATTR_NO_WARN is only implemented on PowerPC. 123 124 DMA_ATTR_PRIVILEGED 125 ------------------- 126 127 Some advanced peripherals such as remote processors and GPUs perform 128 accesses to DMA buffers in both privileged "supervisor" and unprivileged 129 "user" modes. This attribute is used to indicate to the DMA-mapping 130 subsystem that the buffer is fully accessible at the elevated privilege 131 level (and ideally inaccessible or at least read-only at the 132 lesser-privileged levels).
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