1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,coresight-catu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Arm Coresight Address Translation Unit (CATU)
8
9 maintainers:
10 - Mathieu Poirier <mathieu.poirier@linaro.org>
11 - Mike Leach <mike.leach@linaro.org>
12 - Leo Yan <leo.yan@linaro.org>
13 - Suzuki K Poulose <suzuki.poulose@arm.com>
14
15 description: |
16 CoreSight components are compliant with the ARM CoreSight architecture
17 specification and can be connected in various topologies to suit a particular
18 SoCs tracing needs. These trace components can generally be classified as
19 sinks, links and sources. Trace data produced by one or more sources flows
20 through the intermediate links connecting the source to the currently selected
21 sink.
22
23 The CoreSight Address Translation Unit (CATU) translates addresses between an
24 AXI master and system memory. The CATU is normally used along with the TMC to
25 implement scattering of virtual trace buffers in physical memory. The CATU
26 translates contiguous Virtual Addresses (VAs) from an AXI master into
27 non-contiguous Physical Addresses (PAs) that are intended for system memory.
28
29 # Need a custom select here or 'arm,primecell' will match on lots of nodes
30 select:
31 properties:
32 compatible:
33 contains:
34 const: arm,coresight-catu
35 required:
36 - compatible
37
38 allOf:
39 - $ref: /schemas/arm/primecell.yaml#
40
41 properties:
42 compatible:
43 items:
44 - const: arm,coresight-catu
45 - const: arm,primecell
46
47 reg:
48 maxItems: 1
49
50 clocks:
51 minItems: 1
52 maxItems: 2
53
54 clock-names:
55 minItems: 1
56 items:
57 - const: apb_pclk
58 - const: atclk
59
60 interrupts:
61 maxItems: 1
62 description: Address translation error interrupt
63
64 power-domains:
65 maxItems: 1
66
67 in-ports:
68 $ref: /schemas/graph.yaml#/properties/ports
69 additionalProperties: false
70
71 properties:
72 port:
73 description: AXI Slave connected to another Coresight component
74 $ref: /schemas/graph.yaml#/properties/port
75
76 required:
77 - compatible
78 - reg
79 - clocks
80 - clock-names
81 - in-ports
82
83 unevaluatedProperties: false
84
85 examples:
86 - |
87 #include <dt-bindings/interrupt-controller/arm-gic.h>
88 catu@207e0000 {
89 compatible = "arm,coresight-catu", "arm,primecell";
90 reg = <0x207e0000 0x1000>;
91
92 clocks = <&oscclk6a>;
93 clock-names = "apb_pclk";
94
95 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
96 in-ports {
97 port {
98 catu_in_port: endpoint {
99 remote-endpoint = <&etr_out_port>;
100 };
101 };
102 };
103 };
104 ...
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