1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,coresight-etm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Arm CoreSight Embedded Trace MacroCell
8
9 maintainers:
10 - Mathieu Poirier <mathieu.poirier@linaro.org>
11 - Mike Leach <mike.leach@linaro.org>
12 - Leo Yan <leo.yan@linaro.org>
13 - Suzuki K Poulose <suzuki.poulose@arm.com>
14
15 description: |
16 CoreSight components are compliant with the ARM CoreSight architecture
17 specification and can be connected in various topologies to suit a particular
18 SoCs tracing needs. These trace components can generally be classified as
19 sinks, links and sources. Trace data produced by one or more sources flows
20 through the intermediate links connecting the source to the currently selected
21 sink.
22
23 The Embedded Trace Macrocell (ETM) is a real-time trace module providing
24 instruction and data tracing of a processor.
25
26 select:
27 properties:
28 compatible:
29 contains:
30 enum:
31 - arm,coresight-etm3x
32 - arm,coresight-etm4x
33 - arm,coresight-etm4x-sysreg
34 required:
35 - compatible
36
37 allOf:
38 - if:
39 not:
40 properties:
41 compatible:
42 contains:
43 const: arm,coresight-etm4x-sysreg
44 then:
45 $ref: /schemas/arm/primecell.yaml#
46 required:
47 - reg
48
49 properties:
50 compatible:
51 oneOf:
52 - description:
53 Embedded Trace Macrocell with memory mapped access.
54 items:
55 - enum:
56 - arm,coresight-etm3x
57 - arm,coresight-etm4x
58 - const: arm,primecell
59 - description:
60 Embedded Trace Macrocell (version 4.x), with system register access only
61 const: arm,coresight-etm4x-sysreg
62
63 reg:
64 maxItems: 1
65
66 clocks:
67 minItems: 1
68 maxItems: 2
69
70 clock-names:
71 minItems: 1
72 items:
73 - const: apb_pclk
74 - const: atclk
75
76 power-domains:
77 maxItems: 1
78
79 arm,coresight-loses-context-with-cpu:
80 type: boolean
81 description:
82 Indicates that the hardware will lose register context on CPU power down
83 (e.g. CPUIdle). An example of where this may be needed are systems which
84 contain a coresight component and CPU in the same power domain. When the
85 CPU powers down the coresight component also powers down and loses its
86 context.
87
88 arm,cp14:
89 type: boolean
90 description:
91 Must be present if the system accesses ETM/PTM management registers via
92 co-processor 14.
93
94 qcom,skip-power-up:
95 type: boolean
96 description:
97 Indicates that an implementation can skip powering up the trace unit.
98 TRCPDCR.PU does not have to be set on Qualcomm Technologies Inc. systems
99 since ETMs are in the same power domain as their CPU cores. This property
100 is required to identify such systems with hardware errata where the CPU
101 watchdog counter is stopped when TRCPDCR.PU is set.
102
103 cpu:
104 description:
105 phandle to the cpu this ETM is bound to.
106 $ref: /schemas/types.yaml#/definitions/phandle
107
108 out-ports:
109 $ref: /schemas/graph.yaml#/properties/ports
110 additionalProperties: false
111
112 properties:
113 port:
114 description: Output connection from the ETM to CoreSight Trace bus.
115 $ref: /schemas/graph.yaml#/properties/port
116
117 required:
118 - compatible
119 - clocks
120 - clock-names
121 - cpu
122 - out-ports
123
124 unevaluatedProperties: false
125
126 examples:
127 - |
128 ptm@2201c000 {
129 compatible = "arm,coresight-etm3x", "arm,primecell";
130 reg = <0x2201c000 0x1000>;
131
132 cpu = <&cpu0>;
133 clocks = <&oscclk6a>;
134 clock-names = "apb_pclk";
135 out-ports {
136 port {
137 ptm0_out_port: endpoint {
138 remote-endpoint = <&funnel_in_port0>;
139 };
140 };
141 };
142 };
143
144 ptm@2201d000 {
145 compatible = "arm,coresight-etm3x", "arm,primecell";
146 reg = <0x2201d000 0x1000>;
147
148 cpu = <&cpu1>;
149 clocks = <&oscclk6a>;
150 clock-names = "apb_pclk";
151 out-ports {
152 port {
153 ptm1_out_port: endpoint {
154 remote-endpoint = <&funnel_in_port1>;
155 };
156 };
157 };
158 };
159 ...
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