1 Freescale Vybrid Miscellaneous System Control - Interrupt Router
2
3 The MSCM IP contains multiple sub modules, this binding describes the second
4 block of registers which control the interrupt router. The interrupt router
5 allows to configure the recipient of each peripheral interrupt. Furthermore
6 it controls the directed processor interrupts. The module is available in all
7 Vybrid SoC's but is only really useful in dual core configurations (VF6xx
8 which comes with a Cortex-A5/Cortex-M4 combination).
9
10 Required properties:
11 - compatible: "fsl,vf610-mscm-ir"
12 - reg: the register range of the MSCM Interrupt Router
13 - fsl,cpucfg: The handle to the MSCM CPU configuration node, required
14 to get the current CPU ID
15 - interrupt-controller: Identifies the node as an interrupt controller
16 - #interrupt-cells: Two cells, interrupt number and cells.
17 The hardware interrupt number according to interrupt
18 assignment of the interrupt router is required.
19 Flags get passed only when using GIC as parent. Flags
20 encoding as documented by the GIC bindings.
21
22 Example:
23 mscm_ir: interrupt-controller@40001800 {
24 compatible = "fsl,vf610-mscm-ir";
25 reg = <0x40001800 0x400>;
26 fsl,cpucfg = <&mscm_cpucfg>;
27 interrupt-controller;
28 #interrupt-cells = <2>;
29 interrupt-parent = <&intc>;
30 }
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.