1 Some socs have a large number of interrupts requests to service
2 the needs of its many peripherals and subsystems. All of the
3 interrupt lines from the subsystems are not needed at the same
4 time, so they have to be muxed to the irq-controller appropriately.
5 In such places a interrupt controllers are preceded by an CROSSBAR
6 that provides flexibility in muxing the device requests to the controller
7 inputs.
8
9 Required properties:
10 - compatible : Should be "ti,irq-crossbar"
11 - reg: Base address and the size of the crossbar registers.
12 - interrupt-controller: indicates that this block is an interrupt controller.
13 - ti,max-irqs: Total number of irqs available at the parent interrupt controller.
14 - ti,max-crossbar-sources: Maximum number of crossbar sources that can be routed.
15 - ti,reg-size: Size of a individual register in bytes. Every individual
16 register is assumed to be of same size. Valid sizes are 1, 2, 4.
17 - ti,irqs-reserved: List of the reserved irq lines that are not muxed using
18 crossbar. These interrupt lines are reserved in the soc,
19 so crossbar bar driver should not consider them as free
20 lines.
21
22 Optional properties:
23 - ti,irqs-skip: This is similar to "ti,irqs-reserved", but these are for
24 SOC-specific hard-wiring of those irqs which unexpectedly bypasses the
25 crossbar. These irqs have a crossbar register, but still cannot be used.
26
27 - ti,irqs-safe-map: integer which maps to a safe configuration to use
28 when the interrupt controller irq is unused (when not provided, default is 0)
29
30 Examples:
31 crossbar_mpu: crossbar@4a002a48 {
32 compatible = "ti,irq-crossbar";
33 reg = <0x4a002a48 0x130>;
34 ti,max-irqs = <160>;
35 ti,max-crossbar-sources = <400>;
36 ti,reg-size = <2>;
37 ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
38 ti,irqs-skip = <10 133 139 140>;
39 };
40
41 Consumer:
42 ========
43 See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt and
44 Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml for
45 further details.
46
47 An interrupt consumer on an SoC using crossbar will use:
48 interrupts = <GIC_SPI request_number interrupt_level>
49
50 Example:
51 device_x@4a023000 {
52 /* Crossbar 8 used */
53 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
54 ...
55 };
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