1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/ata/mediatek,mtk-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: MediaTek Serial ATA controller
8
9 maintainers:
10 - Ryder Lee <ryder.lee@mediatek.com>
11
12 allOf:
13 - $ref: ahci-common.yaml#
14
15 properties:
16 compatible:
17 items:
18 - enum:
19 - mediatek,mt7622-ahci
20 - const: mediatek,mtk-ahci
21
22 reg:
23 maxItems: 1
24
25 interrupts:
26 maxItems: 1
27
28 interrupt-names:
29 const: hostc
30
31 clocks:
32 maxItems: 5
33
34 clock-names:
35 items:
36 - const: ahb
37 - const: axi
38 - const: asic
39 - const: rbc
40 - const: pm
41
42 power-domains:
43 maxItems: 1
44
45 resets:
46 maxItems: 3
47
48 reset-names:
49 items:
50 - const: axi
51 - const: sw
52 - const: reg
53
54 mediatek,phy-mode:
55 description: System controller phandle, used to enable SATA function
56 $ref: /schemas/types.yaml#/definitions/phandle
57
58 required:
59 - reg
60 - interrupts
61 - interrupt-names
62 - clocks
63 - clock-names
64 - phys
65 - phy-names
66 - ports-implemented
67
68 unevaluatedProperties: false
69
70 examples:
71 - |
72 #include <dt-bindings/clock/mt7622-clk.h>
73 #include <dt-bindings/interrupt-controller/arm-gic.h>
74 #include <dt-bindings/phy/phy.h>
75 #include <dt-bindings/power/mt7622-power.h>
76 #include <dt-bindings/reset/mt7622-reset.h>
77
78 sata@1a200000 {
79 compatible = "mediatek,mt7622-ahci", "mediatek,mtk-ahci";
80 reg = <0x1a200000 0x1100>;
81 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
82 interrupt-names = "hostc";
83 clocks = <&pciesys CLK_SATA_AHB_EN>,
84 <&pciesys CLK_SATA_AXI_EN>,
85 <&pciesys CLK_SATA_ASIC_EN>,
86 <&pciesys CLK_SATA_RBC_EN>,
87 <&pciesys CLK_SATA_PM_EN>;
88 clock-names = "ahb", "axi", "asic", "rbc", "pm";
89 phys = <&u3port1 PHY_TYPE_SATA>;
90 phy-names = "sata-phy";
91 ports-implemented = <0x1>;
92 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
93 resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
94 <&pciesys MT7622_SATA_PHY_SW_RST>,
95 <&pciesys MT7622_SATA_PHY_REG_RST>;
96 reset-names = "axi", "sw", "reg";
97 mediatek,phy-mode = <&pciesys>;
98 };
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