TOMOYO Linux Cross Reference
Linux/Documentation/devicetree/bindings/ata/snps,dwc-ahci-common.yaml

   # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   %YAML 1.2
   ---
   $id: http://devicetree.org/schemas/ata/snps,dwc-ahci-common.yaml#
   $schema: http://devicetree.org/meta-schemas/core.yaml#
   
   title: Synopsys DWC AHCI SATA controller properties
   
   maintainers:
    - Serge Semin <fancer.lancer@gmail.com>
  
  description:
    This document defines device tree schema for the generic Synopsys DWC
    AHCI controller properties.
  
  select: false
  
  allOf:
    - $ref: ahci-common.yaml#
  
  properties:
    reg:
      maxItems: 1
  
    interrupts:
      maxItems: 1
  
    clocks:
      description:
        Basic DWC AHCI SATA clock sources like application AXI/AHB BIU clock,
        PM-alive clock, RxOOB detection clock, embedded PHYs reference (Rx/Tx)
        clock, etc.
      minItems: 1
      maxItems: 6
  
    clock-names:
      minItems: 1
      maxItems: 6
      items:
        oneOf:
          - description: Application APB/AHB/AXI BIU clock
            enum:
              - pclk
              - aclk
              - hclk
              - sata
          - description: Power Module keep-alive clock
            const: pmalive
          - description: RxOOB detection clock
            const: rxoob
          - description: PHY Transmit Clock
            const: asic
          - description: PHY Receive Clock
            const: rbc
          - description: SATA Ports reference clock
            const: ref
  
    resets:
      description:
        At least basic application and reference clock domains resets are
        normally supported by the DWC AHCI SATA controller.
      minItems: 1
      maxItems: 4
  
    reset-names:
      minItems: 1
      maxItems: 4
      items:
        oneOf:
          - description: Application AHB/AXI BIU clock domain reset control
            enum:
              - arst
              - hrst
          - description: Power Module keep-alive clock domain reset control
            const: pmalive
          - description: RxOOB detection clock domain reset control
            const: rxoob
          - description: Reference clock domain reset control
            const: ref
  
  patternProperties:
    "^sata-port@[0-9a-e]$":
      $ref: '#/$defs/dwc-ahci-port'
  
  additionalProperties: true
  
  $defs:
    dwc-ahci-port:
      $ref: /schemas/ata/ahci-common.yaml#/$defs/ahci-port
  
      properties:
        reg:
          minimum: 0
          maximum: 7
  
        snps,tx-ts-max:
          $ref: /schemas/types.yaml#/definitions/uint32
          description: Maximal size of Tx DMA transactions in FIFO words
          enum: [ 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024 ]
 
       snps,rx-ts-max:
         $ref: /schemas/types.yaml#/definitions/uint32
         description: Maximal size of Rx DMA transactions in FIFO words
         enum: [ 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024 ]
 
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