1 Driver for ARM AXI Bus with Broadcom Plugins (bcma)
2
3 Required properties:
4
5 - compatible : brcm,bus-axi
6
7 - reg : iomem address range of chipcommon core
8
9 The cores on the AXI bus are automatically detected by bcma with the
10 memory ranges they are using and they get registered afterwards.
11 Automatic detection of the IRQ number is not working on
12 BCM47xx/BCM53xx ARM SoCs. To assign IRQ numbers to the cores, provide
13 them manually through device tree. Use an interrupt-map to specify the
14 IRQ used by the devices on the bus. The first address is just an index,
15 because we do not have any special register.
16
17 The top-level axi bus may contain children representing attached cores
18 (devices). This is needed since some hardware details can't be auto
19 detected (e.g. IRQ numbers). Also some of the cores may be responsible
20 for extra things, e.g. ChipCommon providing access to the GPIO chip.
21
22 Example:
23
24 axi@18000000 {
25 compatible = "brcm,bus-axi";
26 reg = <0x18000000 0x1000>;
27 ranges = <0x00000000 0x18000000 0x00100000>;
28 #address-cells = <1>;
29 #size-cells = <1>;
30 #interrupt-cells = <1>;
31 interrupt-map-mask = <0x000fffff 0xffff>;
32 interrupt-map =
33 /* Ethernet Controller 0 */
34 <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
35
36 /* Ethernet Controller 1 */
37 <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
38
39 /* PCIe Controller 0 */
40 <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
41 <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
42 <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
43 <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
44 <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
45 <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
46
47 chipcommon {
48 reg = <0x00000000 0x1000>;
49
50 gpio-controller;
51 #gpio-cells = <2>;
52 };
53 };
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