1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/bus/socionext,uniphier-system-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: UniPhier System Bus
8
9 description: |
10 The UniPhier System Bus is an external bus that connects on-board devices to
11 the UniPhier SoC. It is a simple (semi-)parallel bus with address, data, and
12 some control signals. It supports up to 8 banks (chip selects).
13
14 Before any access to the bus, the bus controller must be configured; the bus
15 controller registers provide the control for the translation from the offset
16 within each bank to the CPU-viewed address. The needed setup includes the
17 base address, the size of each bank. Optionally, some timing parameters can
18 be optimized for faster bus access.
19
20 maintainers:
21 - Masahiro Yamada <yamada.masahiro@socionext.com>
22
23 properties:
24 compatible:
25 const: socionext,uniphier-system-bus
26
27 reg:
28 maxItems: 1
29
30 "#address-cells":
31 description: |
32 The first cell is the bank number (chip select).
33 The second cell is the address offset within the bank.
34 const: 2
35
36 "#size-cells":
37 const: 1
38
39 ranges:
40 description: |
41 Provide address translation from the System Bus to the parent bus.
42
43 Note:
44 The address region(s) that can be assigned for the System Bus is
45 implementation defined. Some SoCs can use 0x00000000-0x0fffffff and
46 0x40000000-0x4fffffff, while other SoCs only 0x40000000-0x4fffffff.
47 There might be additional limitations depending on SoCs and the boot mode.
48 The address translation is arbitrary as long as the banks are assigned in
49 the supported address space with the required alignment and they do not
50 overlap one another.
51
52 For example, it is possible to map:
53 bank 0 to 0x42000000-0x43ffffff, bank 5 to 0x46000000-0x46ffffff
54 It is also possible to map:
55 bank 0 to 0x48000000-0x49ffffff, bank 5 to 0x44000000-0x44ffffff
56 There is no reason to stick to a particular translation mapping, but the
57 "ranges" property should provide a "reasonable" default that is known to
58 work. The software should initialize the bus controller according to it.
59
60 patternProperties:
61 "^.*@[1-5],[1-9a-f][0-9a-f]+$":
62 description: Devices attached to chip selects
63 type: object
64
65 required:
66 - compatible
67 - reg
68 - "#address-cells"
69 - "#size-cells"
70 - ranges
71
72 additionalProperties: false
73
74 examples:
75 - |
76 // In this example,
77 // - the Ethernet device is connected at the offset 0x01f00000 of CS1 and
78 // mapped to 0x43f00000 of the parent bus.
79 // - the UART device is connected at the offset 0x00200000 of CS5 and
80 // mapped to 0x46200000 of the parent bus.
81
82 system-bus@58c00000 {
83 compatible = "socionext,uniphier-system-bus";
84 reg = <0x58c00000 0x400>;
85 #address-cells = <2>;
86 #size-cells = <1>;
87 ranges = <1 0x00000000 0x42000000 0x02000000>,
88 <5 0x00000000 0x46000000 0x01000000>;
89
90 ethernet@1,1f00000 {
91 compatible = "smsc,lan9115";
92 reg = <1 0x01f00000 0x1000>;
93 interrupts = <0 48 4>;
94 phy-mode = "mii";
95 };
96
97 serial@5,200000 {
98 compatible = "ns16550a";
99 reg = <5 0x00200000 0x20>;
100 interrupts = <0 49 4>;
101 clock-frequency = <12288000>;
102 };
103 };
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