1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 # Copyright (C) 2020 SiFive, Inc.
3 %YAML 1.2
4 ---
5 $id: http://devicetree.org/schemas/cache/sifive,ccache0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
7
8 title: SiFive Composable Cache Controller
9
10 maintainers:
11 - Paul Walmsley <paul.walmsley@sifive.com>
12
13 description:
14 The SiFive Composable Cache Controller is used to provide access to fast copies
15 of memory for masters in a Core Complex. The Composable Cache Controller also
16 acts as directory-based coherency manager.
17 All the properties in ePAPR/DeviceTree specification applies for this platform.
18
19 select:
20 properties:
21 compatible:
22 contains:
23 enum:
24 - sifive,ccache0
25 - sifive,fu540-c000-ccache
26 - sifive,fu740-c000-ccache
27
28 required:
29 - compatible
30
31 properties:
32 compatible:
33 oneOf:
34 - items:
35 - enum:
36 - sifive,ccache0
37 - sifive,fu540-c000-ccache
38 - sifive,fu740-c000-ccache
39 - const: cache
40 - items:
41 - enum:
42 - starfive,jh7100-ccache
43 - starfive,jh7110-ccache
44 - const: sifive,ccache0
45 - const: cache
46 - items:
47 - const: microchip,mpfs-ccache
48 - const: sifive,fu540-c000-ccache
49 - const: cache
50
51 cache-block-size:
52 const: 64
53
54 cache-level:
55 enum: [2, 3]
56
57 cache-sets:
58 enum: [1024, 2048]
59
60 cache-size:
61 const: 2097152
62
63 cache-unified: true
64
65 interrupts:
66 minItems: 3
67 items:
68 - description: DirError interrupt
69 - description: DataError interrupt
70 - description: DataFail interrupt
71 - description: DirFail interrupt
72
73 reg:
74 maxItems: 1
75
76 next-level-cache: true
77
78 memory-region:
79 maxItems: 1
80 description: |
81 The reference to the reserved-memory for the L2 Loosely Integrated Memory region.
82 The reserved memory node should be defined as per the bindings in reserved-memory.txt.
83
84 allOf:
85 - $ref: /schemas/cache-controller.yaml#
86
87 - if:
88 properties:
89 compatible:
90 contains:
91 enum:
92 - sifive,fu740-c000-ccache
93 - starfive,jh7100-ccache
94 - starfive,jh7110-ccache
95 - microchip,mpfs-ccache
96
97 then:
98 properties:
99 interrupts:
100 description: |
101 Must contain entries for DirError, DataError, DataFail, DirFail signals.
102 minItems: 4
103
104 else:
105 properties:
106 interrupts:
107 description: |
108 Must contain entries for DirError, DataError and DataFail signals.
109 maxItems: 3
110
111 - if:
112 properties:
113 compatible:
114 contains:
115 enum:
116 - sifive,fu740-c000-ccache
117 - starfive,jh7100-ccache
118 - starfive,jh7110-ccache
119
120 then:
121 properties:
122 cache-sets:
123 const: 2048
124
125 else:
126 properties:
127 cache-sets:
128 const: 1024
129
130 - if:
131 properties:
132 compatible:
133 contains:
134 const: sifive,ccache0
135
136 then:
137 properties:
138 cache-level:
139 enum: [2, 3]
140
141 else:
142 properties:
143 cache-level:
144 const: 2
145
146 additionalProperties: false
147
148 required:
149 - compatible
150 - cache-block-size
151 - cache-level
152 - cache-sets
153 - cache-size
154 - cache-unified
155 - interrupts
156 - reg
157
158 examples:
159 - |
160 cache-controller@2010000 {
161 compatible = "sifive,fu540-c000-ccache", "cache";
162 cache-block-size = <64>;
163 cache-level = <2>;
164 cache-sets = <1024>;
165 cache-size = <2097152>;
166 cache-unified;
167 reg = <0x2010000 0x1000>;
168 interrupt-parent = <&plic0>;
169 interrupts = <1>,
170 <2>,
171 <3>;
172 next-level-cache = <&L25>;
173 memory-region = <&l2_lim>;
174 };
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