1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/clock/adi,axi-clkgen.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Analog Devices AXI clkgen pcore clock generator
8
9 maintainers:
10 - Lars-Peter Clausen <lars@metafoo.de>
11 - Michael Hennerich <michael.hennerich@analog.com>
12
13 description: |
14 The axi_clkgen IP core is a software programmable clock generator,
15 that can be synthesized on various FPGA platforms.
16
17 Link: https://wiki.analog.com/resources/fpga/docs/axi_clkgen
18
19 properties:
20 compatible:
21 enum:
22 - adi,axi-clkgen-2.00.a
23 - adi,zynqmp-axi-clkgen-2.00.a
24
25 clocks:
26 description:
27 Specifies the reference clock(s) from which the output frequency is
28 derived. This must either reference one clock if only the first clock
29 input is connected or two if both clock inputs are connected.
30 minItems: 1
31 maxItems: 2
32
33 '#clock-cells':
34 const: 0
35
36 reg:
37 maxItems: 1
38
39 required:
40 - compatible
41 - reg
42 - clocks
43 - '#clock-cells'
44
45 additionalProperties: false
46
47 examples:
48 - |
49 clock-controller@ff000000 {
50 compatible = "adi,axi-clkgen-2.00.a";
51 #clock-cells = <0>;
52 reg = <0xff000000 0x1000>;
53 clocks = <&osc 1>;
54 };
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