1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/clock/fsl,qoriq-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Clock Block on Freescale QorIQ Platforms
8
9 maintainers:
10 - Frank Li <Frank.Li@nxp.com>
11
12 description: |
13 Freescale QorIQ chips take primary clocking input from the external
14 SYSCLK signal. The SYSCLK input (frequency) is multiplied using
15 multiple phase locked loops (PLL) to create a variety of frequencies
16 which can then be passed to a variety of internal logic, including
17 cores and peripheral IP blocks.
18 Please refer to the Reference Manual for details.
19
20 All references to "1.0" and "2.0" refer to the QorIQ chassis version to
21 which the chip complies.
22
23 Chassis Version Example Chips
24 --------------- -------------
25 1.0 p4080, p5020, p5040
26 2.0 t4240
27
28 Clock Provider
29
30 The clockgen node should act as a clock provider, though in older device
31 trees the children of the clockgen node are the clock providers.
32
33 properties:
34 compatible:
35 oneOf:
36 - items:
37 - enum:
38 - fsl,p2041-clockgen
39 - fsl,p3041-clockgen
40 - fsl,p4080-clockgen
41 - fsl,p5020-clockgen
42 - fsl,p5040-clockgen
43 - const: fsl,qoriq-clockgen-1.0
44 - items:
45 - enum:
46 - fsl,t1023-clockgen
47 - fsl,t1024-clockgen
48 - fsl,t1040-clockgen
49 - fsl,t1042-clockgen
50 - fsl,t2080-clockgen
51 - fsl,t2081-clockgen
52 - fsl,t4240-clockgen
53 - const: fsl,qoriq-clockgen-2.0
54 - items:
55 - enum:
56 - fsl,b4420-clockgen
57 - fsl,b4860-clockgen
58 - const: fsl,b4-clockgen
59 - items:
60 - enum:
61 - fsl,ls1012a-clockgen
62 - fsl,ls1021a-clockgen
63 - fsl,ls1028a-clockgen
64 - fsl,ls1043a-clockgen
65 - fsl,ls1046a-clockgen
66 - fsl,ls1088a-clockgen
67 - fsl,ls2080a-clockgen
68 - fsl,lx2160a-clockgen
69
70 reg:
71 maxItems: 1
72
73 ranges: true
74
75 '#address-cells':
76 const: 1
77
78 '#size-cells':
79 const: 1
80
81 '#clock-cells':
82 const: 2
83 description: |
84 The first cell of the clock specifier is the clock type, and the
85 second cell is the clock index for the specified type.
86
87 Type# Name Index Cell
88 0 sysclk must be 0
89 1 cmux index (n in CLKCnCSR)
90 2 hwaccel index (n in CLKCGnHWACSR)
91 3 fman 0 for fm1, 1 for fm2
92 4 platform pll n=pll/(n+1). For example, when n=1,
93 that means output_freq=PLL_freq/2.
94 5 coreclk must be 0
95
96 clock-frequency:
97 description: Input system clock frequency (SYSCLK)
98
99 clocks:
100 items:
101 - description:
102 sysclk may be provided as an input clock. Either clock-frequency
103 or clocks must be provided.
104 - description:
105 A second input clock, called "coreclk", may be provided if
106 core PLLs are based on a different input clock from the
107 platform PLL.
108 minItems: 1
109
110 clock-names:
111 items:
112 - const: sysclk
113 - const: coreclk
114
115 patternProperties:
116 '^mux[0-9]@[a-f0-9]+$':
117 deprecated: true
118 $ref: fsl,qoriq-clock-legacy.yaml
119
120 '^sysclk(-[a-z0-9]+)?$':
121 deprecated: true
122 $ref: fsl,qoriq-clock-legacy.yaml
123
124 '^pll[0-9]@[a-f0-9]+$':
125 deprecated: true
126 $ref: fsl,qoriq-clock-legacy.yaml
127
128 '^platform\-pll@[a-f0-9]+$':
129 deprecated: true
130 $ref: fsl,qoriq-clock-legacy.yaml
131
132 required:
133 - compatible
134 - reg
135 - '#clock-cells'
136
137 additionalProperties: false
138
139 examples:
140 - |
141 /* clock provider example */
142 global-utilities@e1000 {
143 compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
144 reg = <0xe1000 0x1000>;
145 clock-frequency = <133333333>;
146 #clock-cells = <2>;
147 };
148
149 - |
150 /* Legacy example */
151 global-utilities@e1000 {
152 compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
153 reg = <0xe1000 0x1000>;
154 ranges = <0x0 0xe1000 0x1000>;
155 clock-frequency = <133333333>;
156 #address-cells = <1>;
157 #size-cells = <1>;
158 #clock-cells = <2>;
159
160 sysclk: sysclk {
161 compatible = "fsl,qoriq-sysclk-1.0";
162 clock-output-names = "sysclk";
163 #clock-cells = <0>;
164 };
165
166 pll0: pll0@800 {
167 compatible = "fsl,qoriq-core-pll-1.0";
168 reg = <0x800 0x4>;
169 #clock-cells = <1>;
170 clocks = <&sysclk>;
171 clock-output-names = "pll0", "pll0-div2";
172 };
173
174 pll1: pll1@820 {
175 compatible = "fsl,qoriq-core-pll-1.0";
176 reg = <0x820 0x4>;
177 #clock-cells = <1>;
178 clocks = <&sysclk>;
179 clock-output-names = "pll1", "pll1-div2";
180 };
181
182 mux0: mux0@0 {
183 compatible = "fsl,qoriq-core-mux-1.0";
184 reg = <0x0 0x4>;
185 #clock-cells = <0>;
186 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
187 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
188 clock-output-names = "cmux0";
189 };
190
191 mux1: mux1@20 {
192 compatible = "fsl,qoriq-core-mux-1.0";
193 reg = <0x20 0x4>;
194 #clock-cells = <0>;
195 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
196 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
197 clock-output-names = "cmux1";
198 };
199
200 platform-pll@c00 {
201 #clock-cells = <1>;
202 reg = <0xc00 0x4>;
203 compatible = "fsl,qoriq-platform-pll-1.0";
204 clocks = <&sysclk>;
205 clock-output-names = "platform-pll", "platform-pll-div2";
206 };
207 };
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