1 * HiSilicon Clock and Reset Generator(CRG)
2
3 The CRG module provides clock and reset signals to various
4 modules within the SoC.
5
6 This binding uses the following bindings:
7 Documentation/devicetree/bindings/clock/clock-bindings.txt
8 Documentation/devicetree/bindings/reset/reset.txt
9
10 Required Properties:
11
12 - compatible: should be one of the following.
13 - "hisilicon,hi3516cv300-crg"
14 - "hisilicon,hi3516cv300-sysctrl"
15 - "hisilicon,hi3519-crg"
16 - "hisilicon,hi3798cv200-crg"
17 - "hisilicon,hi3798cv200-sysctrl"
18
19 - reg: physical base address of the controller and length of memory mapped
20 region.
21
22 - #clock-cells: should be 1.
23
24 Each clock is assigned an identifier and client nodes use this identifier
25 to specify the clock which they consume.
26
27 All these identifier could be found in <dt-bindings/clock/hi3519-clock.h>.
28
29 - #reset-cells: should be 2.
30
31 A reset signal can be controlled by writing a bit register in the CRG module.
32 The reset specifier consists of two cells. The first cell represents the
33 register offset relative to the base address. The second cell represents the
34 bit index in the register.
35
36 Example: CRG nodes
37 CRG: clock-reset-controller@12010000 {
38 compatible = "hisilicon,hi3519-crg";
39 reg = <0x12010000 0x10000>;
40 #clock-cells = <1>;
41 #reset-cells = <2>;
42 };
43
44 Example: consumer nodes
45 i2c0: i2c@12110000 {
46 compatible = "hisilicon,hi3519-i2c";
47 reg = <0x12110000 0x1000>;
48 clocks = <&CRG HI3519_I2C0_RST>;
49 resets = <&CRG 0xe4 0>;
50 };
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