1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/clock/hisilicon,hi3559av100-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Hisilicon SOC Clock for HI3559AV100
8
9 maintainers:
10 - Dongjiu Geng <gengdongjiu@huawei.com>
11
12 description: |
13 Hisilicon SOC clock control module which supports the clocks, resets and
14 power domains on HI3559AV100.
15
16 See also:
17 dt-bindings/clock/hi3559av100-clock.h
18
19 properties:
20 compatible:
21 enum:
22 - hisilicon,hi3559av100-clock
23 - hisilicon,hi3559av100-shub-clock
24
25 reg:
26 minItems: 1
27 maxItems: 2
28
29 '#clock-cells':
30 const: 1
31
32 '#reset-cells':
33 const: 2
34 description: |
35 First cell is reset request register offset.
36 Second cell is bit offset in reset request register.
37
38 required:
39 - compatible
40 - reg
41 - '#clock-cells'
42 - '#reset-cells'
43
44 additionalProperties: false
45
46 examples:
47 - |
48 soc {
49 #address-cells = <2>;
50 #size-cells = <2>;
51
52 clock-controller@12010000 {
53 compatible = "hisilicon,hi3559av100-clock";
54 #clock-cells = <1>;
55 #reset-cells = <2>;
56 reg = <0x0 0x12010000 0x0 0x10000>;
57 };
58 };
59 ...
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