1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/clock/imx8ulp-pcc-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: NXP i.MX8ULP Peripheral Clock Controller(PCC) Module
8
9 maintainers:
10 - Jacky Bai <ping.bai@nxp.com>
11
12 description: |
13 On i.MX8ULP, The clock sources generation, distribution and management is
14 under the control of several CGCs & PCCs modules. The PCC modules control
15 software reset, clock selection, optional division and clock gating mode
16 for peripherals.
17
18 properties:
19 compatible:
20 enum:
21 - fsl,imx8ulp-pcc3
22 - fsl,imx8ulp-pcc4
23 - fsl,imx8ulp-pcc5
24
25 reg:
26 maxItems: 1
27
28 '#clock-cells':
29 const: 1
30
31 '#reset-cells':
32 const: 1
33
34 required:
35 - compatible
36 - reg
37 - '#clock-cells'
38 - '#reset-cells'
39
40 additionalProperties: false
41
42 examples:
43 # Peripheral Clock Control Module node:
44 - |
45 clock-controller@292d0000 {
46 compatible = "fsl,imx8ulp-pcc3";
47 reg = <0x292d0000 0x10000>;
48 #clock-cells = <1>;
49 #reset-cells = <1>;
50 };
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