1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/clock/mediatek,mt7621-sysc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: MT7621 Clock
8
9 maintainers:
10 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
11
12 description: |
13 The MT7621 has a PLL controller from where the cpu clock is provided
14 as well as derived clocks for the bus and the peripherals. It also
15 can gate SoC device clocks.
16
17 Each clock is assigned an identifier and client nodes use this identifier
18 to specify the clock which they consume.
19
20 All these identifiers could be found in:
21 [1]: <include/dt-bindings/clock/mt7621-clk.h>.
22
23 The clocks are provided inside a system controller node.
24
25 This node is also a reset provider for all the peripherals.
26
27 Reset related bits are defined in:
28 [2]: <include/dt-bindings/reset/mt7621-reset.h>.
29
30 properties:
31 compatible:
32 items:
33 - const: mediatek,mt7621-sysc
34 - const: syscon
35
36 reg:
37 maxItems: 1
38
39 "#clock-cells":
40 description:
41 The first cell indicates the clock number, see [1] for available
42 clocks.
43 const: 1
44
45 "#reset-cells":
46 description:
47 The first cell indicates the reset bit within the register, see
48 [2] for available resets.
49 const: 1
50
51 ralink,memctl:
52 $ref: /schemas/types.yaml#/definitions/phandle
53 description:
54 phandle of syscon used to control memory registers
55
56 clock-output-names:
57 maxItems: 8
58
59 required:
60 - compatible
61 - reg
62 - '#clock-cells'
63 - ralink,memctl
64
65 additionalProperties: false
66
67 examples:
68 - |
69 #include <dt-bindings/clock/mt7621-clk.h>
70
71 sysc: sysc@0 {
72 compatible = "mediatek,mt7621-sysc", "syscon";
73 reg = <0x0 0x100>;
74 #clock-cells = <1>;
75 #reset-cells = <1>;
76 ralink,memctl = <&memc>;
77 clock-output-names = "xtal", "cpu", "bus",
78 "50m", "125m", "150m",
79 "250m", "270m";
80 };
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