1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/clock/mediatek,mt8186-sys-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: MediaTek System Clock Controller for MT8186
8
9 maintainers:
10 - Chun-Jie Chen <chun-jie.chen@mediatek.com>
11
12 description: |
13 The clock architecture in MediaTek like below
14 PLLs -->
15 dividers -->
16 muxes
17 -->
18 clock gate
19
20 The apmixedsys provides most of PLLs which generated from SoC 26m.
21 The topckgen provides dividers and muxes which provide the clock source to other IP blocks.
22 The infracfg_ao provides clock gate in peripheral and infrastructure IP blocks.
23 The mcusys provides mux control to select the clock source in AP MCU.
24 The device nodes also provide the system control capacity for configuration.
25
26 properties:
27 compatible:
28 items:
29 - enum:
30 - mediatek,mt8186-mcusys
31 - mediatek,mt8186-topckgen
32 - mediatek,mt8186-infracfg_ao
33 - mediatek,mt8186-apmixedsys
34 - const: syscon
35
36 reg:
37 maxItems: 1
38
39 '#clock-cells':
40 const: 1
41
42 '#reset-cells':
43 const: 1
44
45 required:
46 - compatible
47 - reg
48
49 additionalProperties: false
50
51 examples:
52 - |
53 topckgen: syscon@10000000 {
54 compatible = "mediatek,mt8186-topckgen", "syscon";
55 reg = <0x10000000 0x1000>;
56 #clock-cells = <1>;
57 };
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