1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/clock/mediatek,mt8195-sys-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: MediaTek System Clock Controller for MT8195
8
9 maintainers:
10 - Chun-Jie Chen <chun-jie.chen@mediatek.com>
11
12 description:
13 The clock architecture in Mediatek like below
14 PLLs -->
15 dividers -->
16 muxes
17 -->
18 clock gate
19
20 The apmixedsys provides most of PLLs which generated from SoC 26m.
21 The topckgen provides dividers and muxes which provide the clock source to other IP blocks.
22 The infracfg_ao and pericfg_ao provides clock gate in peripheral and infrastructure IP blocks.
23
24 properties:
25 compatible:
26 items:
27 - enum:
28 - mediatek,mt8195-topckgen
29 - mediatek,mt8195-infracfg_ao
30 - mediatek,mt8195-apmixedsys
31 - mediatek,mt8195-pericfg_ao
32 - const: syscon
33
34 reg:
35 maxItems: 1
36
37 '#clock-cells':
38 const: 1
39
40 '#reset-cells':
41 const: 1
42
43 required:
44 - compatible
45 - reg
46
47 additionalProperties: false
48
49 examples:
50 - |
51 topckgen: syscon@10000000 {
52 compatible = "mediatek,mt8195-topckgen", "syscon";
53 reg = <0x10000000 0x1000>;
54 #clock-cells = <1>;
55 };
56
57 - |
58 infracfg_ao: syscon@10001000 {
59 compatible = "mediatek,mt8195-infracfg_ao", "syscon";
60 reg = <0x10001000 0x1000>;
61 #clock-cells = <1>;
62 };
63
64 - |
65 apmixedsys: syscon@1000c000 {
66 compatible = "mediatek,mt8195-apmixedsys", "syscon";
67 reg = <0x1000c000 0x1000>;
68 #clock-cells = <1>;
69 };
70
71 - |
72 pericfg_ao: syscon@11003000 {
73 compatible = "mediatek,mt8195-pericfg_ao", "syscon";
74 reg = <0x11003000 0x1000>;
75 #clock-cells = <1>;
76 };
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