1 * Core Clock bindings for Marvell MVEBU SoCs
2
3 Marvell MVEBU SoCs usually allow to determine core clock frequencies by
4 reading the Sample-At-Reset (SAR) register. The core clock consumer should
5 specify the desired clock by having the clock ID in its "clocks" phandle cell.
6
7 The following is a list of provided IDs and clock names on Armada 370/XP:
8 0 = tclk (Internal Bus clock)
9 1 = cpuclk (CPU clock)
10 2 = nbclk (L2 Cache clock)
11 3 = hclk (DRAM control clock)
12 4 = dramclk (DDR clock)
13
14 The following is a list of provided IDs and clock names on Armada 375:
15 0 = tclk (Internal Bus clock)
16 1 = cpuclk (CPU clock)
17 2 = l2clk (L2 Cache clock)
18 3 = ddrclk (DDR clock)
19
20 The following is a list of provided IDs and clock names on Armada 380/385:
21 0 = tclk (Internal Bus clock)
22 1 = cpuclk (CPU clock)
23 2 = l2clk (L2 Cache clock)
24 3 = ddrclk (DDR clock)
25
26 The following is a list of provided IDs and clock names on Armada 39x:
27 0 = tclk (Internal Bus clock)
28 1 = cpuclk (CPU clock)
29 2 = nbclk (Coherent Fabric clock)
30 3 = hclk (SDRAM Controller Internal Clock)
31 4 = dclk (SDRAM Interface Clock)
32 5 = refclk (Reference Clock)
33
34 The following is a list of provided IDs and clock names on 98dx3236:
35 0 = tclk (Internal Bus clock)
36 1 = cpuclk (CPU clock)
37 2 = ddrclk (DDR clock)
38 3 = mpll (MPLL Clock)
39
40 The following is a list of provided IDs and clock names on Kirkwood and Dove:
41 0 = tclk (Internal Bus clock)
42 1 = cpuclk (CPU0 clock)
43 2 = l2clk (L2 Cache clock derived from CPU0 clock)
44 3 = ddrclk (DDR controller clock derived from CPU0 clock)
45
46 The following is a list of provided IDs and clock names on Orion5x:
47 0 = tclk (Internal Bus clock)
48 1 = cpuclk (CPU0 clock)
49 2 = ddrclk (DDR controller clock derived from CPU0 clock)
50
51 Required properties:
52 - compatible : shall be one of the following:
53 "marvell,armada-370-core-clock" - For Armada 370 SoC core clocks
54 "marvell,armada-375-core-clock" - For Armada 375 SoC core clocks
55 "marvell,armada-380-core-clock" - For Armada 380/385 SoC core clocks
56 "marvell,armada-390-core-clock" - For Armada 39x SoC core clocks
57 "marvell,armada-xp-core-clock" - For Armada XP SoC core clocks
58 "marvell,mv98dx3236-core-clock" - For 98dx3236 family SoC core clocks
59 "marvell,dove-core-clock" - for Dove SoC core clocks
60 "marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180)
61 "marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC
62 "marvell,mv98dx1135-core-clock" - for Kirkwood 98dx1135 SoC
63 "marvell,mv88f5181-core-clock" - for Orion MV88F5181 SoC
64 "marvell,mv88f5182-core-clock" - for Orion MV88F5182 SoC
65 "marvell,mv88f5281-core-clock" - for Orion MV88F5281 SoC
66 "marvell,mv88f6183-core-clock" - for Orion MV88F6183 SoC
67 - reg : shall be the register address of the Sample-At-Reset (SAR) register
68 - #clock-cells : from common clock binding; shall be set to 1
69
70 Optional properties:
71 - clock-output-names : from common clock binding; allows overwrite default clock
72 output names ("tclk", "cpuclk", "l2clk", "ddrclk")
73
74 Example:
75
76 core_clk: core-clocks@d0214 {
77 compatible = "marvell,dove-core-clock";
78 reg = <0xd0214 0x4>;
79 #clock-cells = <1>;
80 };
81
82 spi0: spi@10600 {
83 compatible = "marvell,orion-spi";
84 /* ... */
85 /* get tclk from core clock provider */
86 clocks = <&core_clk 0>;
87 };
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