1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/clock/nvidia,tegra20-car.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: NVIDIA Tegra Clock and Reset Controller
8
9 maintainers:
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
12
13 description: |
14 The Clock and Reset (CAR) is the HW module responsible for muxing and gating
15 Tegra's clocks, and setting their rates. It comprises CLKGEN and RSTGEN units.
16
17 CLKGEN provides the registers to program the PLLs. It controls most of
18 the clock source programming and most of the clock dividers.
19
20 CLKGEN input signals include the external clock for the reference frequency
21 (12 MHz, 26 MHz) and the external clock for the Real Time Clock (32.768 KHz).
22
23 Outputs from CLKGEN are inputs clock of the h/w blocks in the Tegra system.
24
25 RSTGEN provides the registers needed to control resetting of each block in
26 the Tegra system.
27
28 properties:
29 compatible:
30 enum:
31 - nvidia,tegra20-car
32 - nvidia,tegra30-car
33 - nvidia,tegra114-car
34 - nvidia,tegra210-car
35
36 reg:
37 maxItems: 1
38
39 '#clock-cells':
40 const: 1
41
42 "#reset-cells":
43 const: 1
44
45 patternProperties:
46 "^(sclk)|(pll-[cem])$":
47 type: object
48 properties:
49 compatible:
50 enum:
51 - nvidia,tegra20-sclk
52 - nvidia,tegra30-sclk
53 - nvidia,tegra30-pllc
54 - nvidia,tegra30-plle
55 - nvidia,tegra30-pllm
56
57 operating-points-v2: true
58
59 clocks:
60 items:
61 - description: node's clock
62
63 power-domains:
64 maxItems: 1
65 description: phandle to the core SoC power domain
66
67 required:
68 - compatible
69 - operating-points-v2
70 - clocks
71 - power-domains
72
73 additionalProperties: false
74
75 required:
76 - compatible
77 - reg
78 - '#clock-cells'
79 - "#reset-cells"
80
81 additionalProperties: false
82
83 examples:
84 - |
85 #include <dt-bindings/clock/tegra20-car.h>
86
87 car: clock-controller@60006000 {
88 compatible = "nvidia,tegra20-car";
89 reg = <0x60006000 0x1000>;
90 #clock-cells = <1>;
91 #reset-cells = <1>;
92
93 sclk {
94 compatible = "nvidia,tegra20-sclk";
95 operating-points-v2 = <&opp_table>;
96 clocks = <&tegra_car TEGRA20_CLK_SCLK>;
97 power-domains = <&domain>;
98 };
99 };
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