1 Imagination Technologies Pistachio SoC clock controllers
2 ========================================================
3
4 Pistachio has four clock controllers (core clock, peripheral clock, peripheral
5 general control, and top general control) which are instantiated individually
6 from the device-tree.
7
8 External clocks:
9 ----------------
10
11 There are three external inputs to the clock controllers which should be
12 defined with the following clock-output-names:
13 - "xtal": External 52Mhz oscillator (required)
14 - "audio_clk_in": Alternate audio reference clock (optional)
15 - "enet_clk_in": Alternate ethernet PHY clock (optional)
16
17 Core clock controller:
18 ----------------------
19
20 The core clock controller generates clocks for the CPU, RPU (WiFi + BT
21 co-processor), audio, and several peripherals.
22
23 Required properties:
24 - compatible: Must be "img,pistachio-clk".
25 - reg: Must contain the base address and length of the core clock controller.
26 - #clock-cells: Must be 1. The single cell is the clock identifier.
27 See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.
28 - clocks: Must contain an entry for each clock in clock-names.
29 - clock-names: Must include "xtal" (see "External clocks") and
30 "audio_clk_in_gate", "enet_clk_in_gate" which are generated by the
31 top-level general control.
32
33 Example:
34 clk_core: clock-controller@18144000 {
35 compatible = "img,pistachio-clk";
36 reg = <0x18144000 0x800>;
37 clocks = <&xtal>, <&cr_top EXT_CLK_AUDIO_IN>,
38 <&cr_top EXT_CLK_ENET_IN>;
39 clock-names = "xtal", "audio_clk_in_gate", "enet_clk_in_gate";
40
41 #clock-cells = <1>;
42 };
43
44 Peripheral clock controller:
45 ----------------------------
46
47 The peripheral clock controller generates clocks for the DDR, ROM, and other
48 peripherals. The peripheral system clock ("periph_sys") generated by the core
49 clock controller is the input clock to the peripheral clock controller.
50
51 Required properties:
52 - compatible: Must be "img,pistachio-periph-clk".
53 - reg: Must contain the base address and length of the peripheral clock
54 controller.
55 - #clock-cells: Must be 1. The single cell is the clock identifier.
56 See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.
57 - clocks: Must contain an entry for each clock in clock-names.
58 - clock-names: Must include "periph_sys", the peripheral system clock generated
59 by the core clock controller.
60
61 Example:
62 clk_periph: clock-controller@18144800 {
63 compatible = "img,pistachio-clk-periph";
64 reg = <0x18144800 0x800>;
65 clocks = <&clk_core CLK_PERIPH_SYS>;
66 clock-names = "periph_sys";
67
68 #clock-cells = <1>;
69 };
70
71 Peripheral general control:
72 ---------------------------
73
74 The peripheral general control block generates system interface clocks and
75 resets for various peripherals. It also contains miscellaneous peripheral
76 control registers. The system clock ("sys") generated by the peripheral clock
77 controller is the input clock to the system clock controller.
78
79 Required properties:
80 - compatible: Must include "img,pistachio-periph-cr" and "syscon".
81 - reg: Must contain the base address and length of the peripheral general
82 control registers.
83 - #clock-cells: Must be 1. The single cell is the clock identifier.
84 See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.
85 - clocks: Must contain an entry for each clock in clock-names.
86 - clock-names: Must include "sys", the system clock generated by the peripheral
87 clock controller.
88
89 Example:
90 cr_periph: syscon@18144800 {
91 compatible = "img,pistachio-cr-periph", "syscon";
92 reg = <0x18148000 0x1000>;
93 clocks = <&clock_periph PERIPH_CLK_PERIPH_SYS>;
94 clock-names = "sys";
95
96 #clock-cells = <1>;
97 };
98
99 Top-level general control:
100 --------------------------
101
102 The top-level general control block contains miscellaneous control registers and
103 gates for the external clocks "audio_clk_in" and "enet_clk_in".
104
105 Required properties:
106 - compatible: Must include "img,pistachio-cr-top" and "syscon".
107 - reg: Must contain the base address and length of the top-level
108 control registers.
109 - clocks: Must contain an entry for each clock in clock-names.
110 - clock-names: Two optional clocks, "audio_clk_in" and "enet_clk_in" (see
111 "External clocks").
112 - #clock-cells: Must be 1. The single cell is the clock identifier.
113 See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.
114
115 Example:
116 cr_top: syscon@18144800 {
117 compatible = "img,pistachio-cr-top", "syscon";
118 reg = <0x18149000 0x200>;
119 clocks = <&audio_refclk>, <&ext_enet_in>;
120 clock-names = "audio_clk_in", "enet_clk_in";
121
122 #clock-cells = <1>;
123 };
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