1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Qualcomm Display Clock & Reset Controller on SM8150/SM8250/SM8350
8
9 maintainers:
10 - Jonathan Marek <jonathan@marek.ca>
11
12 description: |
13 Qualcomm display clock control module provides the clocks, resets and power
14 domains on SM8150/SM8250/SM8350.
15
16 See also::
17 include/dt-bindings/clock/qcom,dispcc-sm8150.h
18 include/dt-bindings/clock/qcom,dispcc-sm8250.h
19 include/dt-bindings/clock/qcom,dispcc-sm8350.h
20
21 properties:
22 compatible:
23 enum:
24 - qcom,sc8180x-dispcc
25 - qcom,sm8150-dispcc
26 - qcom,sm8250-dispcc
27 - qcom,sm8350-dispcc
28
29 clocks:
30 minItems: 7
31 items:
32 - description: Board XO source
33 - description: Byte clock from DSI PHY0
34 - description: Pixel clock from DSI PHY0
35 - description: Byte clock from DSI PHY1
36 - description: Pixel clock from DSI PHY1
37 - description: Link clock from DP PHY
38 - description: VCO DIV clock from DP PHY
39 - description: Link clock from eDP PHY
40 - description: VCO DIV clock from eDP PHY
41 - description: Link clock from DP1 PHY
42 - description: VCO DIV clock from DP1 PHY
43 - description: Link clock from DP2 PHY
44 - description: VCO DIV clock from DP2 PHY
45
46 clock-names:
47 minItems: 7
48 items:
49 - const: bi_tcxo
50 - const: dsi0_phy_pll_out_byteclk
51 - const: dsi0_phy_pll_out_dsiclk
52 - const: dsi1_phy_pll_out_byteclk
53 - const: dsi1_phy_pll_out_dsiclk
54 - const: dp_phy_pll_link_clk
55 - const: dp_phy_pll_vco_div_clk
56 - const: edp_phy_pll_link_clk
57 - const: edp_phy_pll_vco_div_clk
58 - const: dptx1_phy_pll_link_clk
59 - const: dptx1_phy_pll_vco_div_clk
60 - const: dptx2_phy_pll_link_clk
61 - const: dptx2_phy_pll_vco_div_clk
62
63 power-domains:
64 description:
65 A phandle and PM domain specifier for the MMCX power domain.
66 maxItems: 1
67
68 required-opps:
69 description:
70 A phandle to an OPP node describing required MMCX performance point.
71 maxItems: 1
72
73 required:
74 - compatible
75 - clocks
76 - clock-names
77 - '#power-domain-cells'
78
79 allOf:
80 - $ref: qcom,gcc.yaml#
81 - if:
82 not:
83 properties:
84 compatible:
85 contains:
86 const: qcom,sc8180x-dispcc
87 then:
88 properties:
89 clocks:
90 maxItems: 7
91 clock-names:
92 maxItems: 7
93
94 unevaluatedProperties: false
95
96 examples:
97 - |
98 #include <dt-bindings/clock/qcom,rpmh.h>
99 #include <dt-bindings/power/qcom,rpmhpd.h>
100 clock-controller@af00000 {
101 compatible = "qcom,sm8250-dispcc";
102 reg = <0x0af00000 0x10000>;
103 clocks = <&rpmhcc RPMH_CXO_CLK>,
104 <&dsi0_phy 0>,
105 <&dsi0_phy 1>,
106 <&dsi1_phy 0>,
107 <&dsi1_phy 1>,
108 <&dp_phy 0>,
109 <&dp_phy 1>;
110 clock-names = "bi_tcxo",
111 "dsi0_phy_pll_out_byteclk",
112 "dsi0_phy_pll_out_dsiclk",
113 "dsi1_phy_pll_out_byteclk",
114 "dsi1_phy_pll_out_dsiclk",
115 "dp_phy_pll_link_clk",
116 "dp_phy_pll_vco_div_clk";
117 #clock-cells = <1>;
118 #reset-cells = <1>;
119 #power-domain-cells = <1>;
120 power-domains = <&rpmhpd RPMHPD_MMCX>;
121 required-opps = <&rpmhpd_opp_low_svs>;
122 };
123 ...
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