1 # SPDX-License-Identifier: GPL-2.0-only
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-sdm845.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Qualcomm Global Clock & Reset Controller on SDM670 and SDM845
8
9 maintainers:
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <quic_tdas@quicinc.com>
12
13 description: |
14 Qualcomm global clock control module provides the clocks, resets and power
15 domains on SDM670 and SDM845
16
17 See also:: include/dt-bindings/clock/qcom,gcc-sdm845.h
18
19 properties:
20 compatible:
21 enum:
22 - qcom,gcc-sdm670
23 - qcom,gcc-sdm845
24
25 clocks:
26 minItems: 3
27 maxItems: 5
28
29 clock-names:
30 minItems: 3
31 maxItems: 5
32
33 power-domains:
34 maxItems: 1
35
36 required:
37 - compatible
38 - '#power-domain-cells'
39
40 allOf:
41 - $ref: qcom,gcc.yaml#
42 - if:
43 properties:
44 compatible:
45 contains:
46 const: qcom,gcc-sdm670
47 then:
48 properties:
49 clocks:
50 items:
51 - description: Board XO source
52 - description: Board active XO source
53 - description: Sleep clock source
54 clock-names:
55 items:
56 - const: bi_tcxo
57 - const: bi_tcxo_ao
58 - const: sleep_clk
59
60 - if:
61 properties:
62 compatible:
63 contains:
64 const: qcom,gcc-sdm845
65 then:
66 properties:
67 clocks:
68 items:
69 - description: Board XO source
70 - description: Board active XO source
71 - description: Sleep clock source
72 - description: PCIE 0 Pipe clock source
73 - description: PCIE 1 Pipe clock source
74 clock-names:
75 items:
76 - const: bi_tcxo
77 - const: bi_tcxo_ao
78 - const: sleep_clk
79 - const: pcie_0_pipe_clk
80 - const: pcie_1_pipe_clk
81
82 unevaluatedProperties: false
83
84 examples:
85 # Example for GCC for SDM845:
86 - |
87 #include <dt-bindings/clock/qcom,rpmh.h>
88 clock-controller@100000 {
89 compatible = "qcom,gcc-sdm845";
90 reg = <0x100000 0x1f0000>;
91 clocks = <&rpmhcc RPMH_CXO_CLK>,
92 <&rpmhcc RPMH_CXO_CLK_A>,
93 <&sleep_clk>,
94 <&pcie0_lane>,
95 <&pcie1_lane>;
96 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "pcie_0_pipe_clk", "pcie_1_pipe_clk";
97 #clock-cells = <1>;
98 #reset-cells = <1>;
99 #power-domain-cells = <1>;
100 };
101 ...
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