1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,ipq5018-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Qualcomm Global Clock & Reset Controller on IPQ5018
8
9 maintainers:
10 - Sricharan Ramabadhran <quic_srichara@quicinc.com>
11
12 description: |
13 Qualcomm global clock control module provides the clocks, resets and power
14 domains on IPQ5018
15
16 See also::
17 include/dt-bindings/clock/qcom,ipq5018-gcc.h
18 include/dt-bindings/reset/qcom,ipq5018-gcc.h
19
20 properties:
21 compatible:
22 const: qcom,gcc-ipq5018
23
24 clocks:
25 items:
26 - description: Board XO source
27 - description: Sleep clock source
28 - description: PCIE20 PHY0 pipe clock source
29 - description: PCIE20 PHY1 pipe clock source
30 - description: USB3 PHY pipe clock source
31 - description: GEPHY RX clock source
32 - description: GEPHY TX clock source
33 - description: UNIPHY RX clock source
34 - description: UNIPHY TX clk source
35
36 '#power-domain-cells': false
37
38 required:
39 - compatible
40 - clocks
41
42 allOf:
43 - $ref: qcom,gcc.yaml#
44
45 unevaluatedProperties: false
46
47 examples:
48 - |
49 clock-controller@1800000 {
50 compatible = "qcom,gcc-ipq5018";
51 reg = <0x01800000 0x80000>;
52 clocks = <&xo_board_clk>,
53 <&sleep_clk>,
54 <&pcie20_phy0_pipe_clk>,
55 <&pcie20_phy1_pipe_clk>,
56 <&usb3_phy0_pipe_clk>,
57 <&gephy_rx_clk>,
58 <&gephy_tx_clk>,
59 <&uniphy_rx_clk>,
60 <&uniphy_tx_clk>;
61 #clock-cells = <1>;
62 #reset-cells = <1>;
63 };
64 ...
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