1 # SPDX-License-Identifier: GPL-2.0-only
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,mmcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Qualcomm Multimedia Clock & Reset Controller
8
9 maintainers:
10 - Jeffrey Hugo <quic_jhugo@quicinc.com>
11 - Taniya Das <quic_tdas@quicinc.com>
12
13 description: |
14 Qualcomm multimedia clock control module provides the clocks, resets and
15 power domains.
16
17 properties:
18 compatible:
19 enum:
20 - qcom,mmcc-apq8064
21 - qcom,mmcc-apq8084
22 - qcom,mmcc-msm8226
23 - qcom,mmcc-msm8660
24 - qcom,mmcc-msm8960
25 - qcom,mmcc-msm8974
26 - qcom,mmcc-msm8992
27 - qcom,mmcc-msm8994
28 - qcom,mmcc-msm8996
29 - qcom,mmcc-msm8998
30 - qcom,mmcc-sdm630
31 - qcom,mmcc-sdm660
32
33 clocks:
34 minItems: 7
35 maxItems: 13
36
37 clock-names:
38 minItems: 7
39 maxItems: 13
40
41 '#clock-cells':
42 const: 1
43
44 '#reset-cells':
45 const: 1
46
47 '#power-domain-cells':
48 const: 1
49
50 reg:
51 maxItems: 1
52
53 protected-clocks:
54 description:
55 Protected clock specifier list as per common clock binding
56
57 vdd-gfx-supply:
58 description:
59 Regulator supply for the GPU_GX GDSC
60
61 required:
62 - compatible
63 - reg
64 - '#clock-cells'
65 - '#reset-cells'
66 - '#power-domain-cells'
67
68 additionalProperties: false
69
70 allOf:
71 - if:
72 properties:
73 compatible:
74 contains:
75 enum:
76 - qcom,mmcc-apq8064
77 - qcom,mmcc-msm8960
78 then:
79 properties:
80 clocks:
81 items:
82 - description: Board PXO source
83 - description: PLL 3 clock
84 - description: PLL 3 Vote clock
85 - description: DSI phy instance 1 dsi clock
86 - description: DSI phy instance 1 byte clock
87 - description: DSI phy instance 2 dsi clock
88 - description: DSI phy instance 2 byte clock
89 - description: HDMI phy PLL clock
90
91 clock-names:
92 items:
93 - const: pxo
94 - const: pll3
95 - const: pll8_vote
96 - const: dsi1pll
97 - const: dsi1pllbyte
98 - const: dsi2pll
99 - const: dsi2pllbyte
100 - const: hdmipll
101
102 - if:
103 properties:
104 compatible:
105 contains:
106 enum:
107 - qcom,mmcc-msm8226
108 then:
109 properties:
110 clocks:
111 items:
112 - description: Board XO source
113 - description: MMSS GPLL0 voted clock
114 - description: GPLL0 voted clock
115 - description: GPLL1 voted clock
116 - description: GFX3D clock source
117 - description: DSI phy instance 0 dsi clock
118 - description: DSI phy instance 0 byte clock
119
120 clock-names:
121 items:
122 - const: xo
123 - const: mmss_gpll0_vote
124 - const: gpll0_vote
125 - const: gpll1_vote
126 - const: gfx3d_clk_src
127 - const: dsi0pll
128 - const: dsi0pllbyte
129
130 - if:
131 properties:
132 compatible:
133 contains:
134 enum:
135 - qcom,mmcc-msm8974
136 then:
137 properties:
138 clocks:
139 items:
140 - description: Board XO source
141 - description: MMSS GPLL0 voted clock
142 - description: GPLL0 voted clock
143 - description: GPLL1 voted clock
144 - description: GFX3D clock source
145 - description: DSI phy instance 0 dsi clock
146 - description: DSI phy instance 0 byte clock
147 - description: DSI phy instance 1 dsi clock
148 - description: DSI phy instance 1 byte clock
149 - description: HDMI phy PLL clock
150 - description: eDP phy PLL link clock
151 - description: eDP phy PLL vco clock
152
153 clock-names:
154 items:
155 - const: xo
156 - const: mmss_gpll0_vote
157 - const: gpll0_vote
158 - const: gpll1_vote
159 - const: gfx3d_clk_src
160 - const: dsi0pll
161 - const: dsi0pllbyte
162 - const: dsi1pll
163 - const: dsi1pllbyte
164 - const: hdmipll
165 - const: edp_link_clk
166 - const: edp_vco_div
167
168 - if:
169 properties:
170 compatible:
171 contains:
172 enum:
173 - qcom,mmcc-apq8084
174 then:
175 properties:
176 clocks:
177 items:
178 - description: Board XO source
179 - description: Board sleep source
180 - description: MMSS GPLL0 voted clock
181 - description: GPLL0 clock
182 - description: GPLL0 voted clock
183 - description: GPLL1 clock
184 - description: DSI phy instance 0 dsi clock
185 - description: DSI phy instance 0 byte clock
186 - description: DSI phy instance 1 dsi clock
187 - description: DSI phy instance 1 byte clock
188 - description: HDMI phy PLL clock
189 - description: eDP phy PLL link clock
190 - description: eDP phy PLL vco clock
191
192 clock-names:
193 items:
194 - const: xo
195 - const: sleep_clk
196 - const: mmss_gpll0_vote
197 - const: gpll0
198 - const: gpll0_vote
199 - const: gpll1
200 - const: dsi0pll
201 - const: dsi0pllbyte
202 - const: dsi1pll
203 - const: dsi1pllbyte
204 - const: hdmipll
205 - const: edp_link_clk
206 - const: edp_vco_div
207
208 - if:
209 properties:
210 compatible:
211 contains:
212 enum:
213 - qcom,mmcc-msm8994
214 - qcom,mmcc-msm8998
215 - qcom,mmcc-sdm630
216 - qcom,mmcc-sdm660
217 then:
218 required:
219 - clocks
220 - clock-names
221
222 - if:
223 properties:
224 compatible:
225 contains:
226 const: qcom,mmcc-msm8994
227 then:
228 properties:
229 clocks:
230 items:
231 - description: Board XO source
232 - description: Global PLL 0 clock
233 - description: MMSS NoC AHB clock
234 - description: GFX3D clock
235 - description: DSI phy instance 0 dsi clock
236 - description: DSI phy instance 0 byte clock
237 - description: DSI phy instance 1 dsi clock
238 - description: DSI phy instance 1 byte clock
239 - description: HDMI phy PLL clock
240
241 clock-names:
242 items:
243 - const: xo
244 - const: gpll0
245 - const: mmssnoc_ahb
246 - const: oxili_gfx3d_clk_src
247 - const: dsi0pll
248 - const: dsi0pllbyte
249 - const: dsi1pll
250 - const: dsi1pllbyte
251 - const: hdmipll
252
253 - if:
254 properties:
255 compatible:
256 contains:
257 const: qcom,mmcc-msm8996
258 then:
259 properties:
260 clocks:
261 items:
262 - description: Board XO source
263 - description: Global PLL 0 clock
264 - description: MMSS NoC AHB clock
265 - description: DSI phy instance 0 dsi clock
266 - description: DSI phy instance 0 byte clock
267 - description: DSI phy instance 1 dsi clock
268 - description: DSI phy instance 1 byte clock
269 - description: HDMI phy PLL clock
270
271 clock-names:
272 items:
273 - const: xo
274 - const: gpll0
275 - const: gcc_mmss_noc_cfg_ahb_clk
276 - const: dsi0pll
277 - const: dsi0pllbyte
278 - const: dsi1pll
279 - const: dsi1pllbyte
280 - const: hdmipll
281
282 - if:
283 properties:
284 compatible:
285 contains:
286 const: qcom,mmcc-msm8998
287 then:
288 properties:
289 clocks:
290 items:
291 - description: Board XO source
292 - description: Global PLL 0 clock
293 - description: DSI phy instance 0 dsi clock
294 - description: DSI phy instance 0 byte clock
295 - description: DSI phy instance 1 dsi clock
296 - description: DSI phy instance 1 byte clock
297 - description: HDMI phy PLL clock
298 - description: DisplayPort phy PLL link clock
299 - description: DisplayPort phy PLL vco clock
300 - description: Global PLL 0 DIV clock
301
302 clock-names:
303 items:
304 - const: xo
305 - const: gpll0
306 - const: dsi0dsi
307 - const: dsi0byte
308 - const: dsi1dsi
309 - const: dsi1byte
310 - const: hdmipll
311 - const: dplink
312 - const: dpvco
313 - const: gpll0_div
314
315 - if:
316 properties:
317 compatible:
318 contains:
319 enum:
320 - qcom,mmcc-sdm630
321 - qcom,mmcc-sdm660
322 then:
323 properties:
324 clocks:
325 items:
326 - description: Board XO source
327 - description: Board sleep source
328 - description: Global PLL 0 clock
329 - description: Global PLL 0 DIV clock
330 - description: DSI phy instance 0 dsi clock
331 - description: DSI phy instance 0 byte clock
332 - description: DSI phy instance 1 dsi clock
333 - description: DSI phy instance 1 byte clock
334 - description: DisplayPort phy PLL link clock
335 - description: DisplayPort phy PLL vco clock
336
337 clock-names:
338 items:
339 - const: xo
340 - const: sleep_clk
341 - const: gpll0
342 - const: gpll0_div
343 - const: dsi0pll
344 - const: dsi0pllbyte
345 - const: dsi1pll
346 - const: dsi1pllbyte
347 - const: dp_link_2x_clk_divsel_five
348 - const: dp_vco_divided_clk_src_mux
349
350 examples:
351 # Example for MMCC for MSM8960:
352 - |
353 clock-controller@4000000 {
354 compatible = "qcom,mmcc-msm8960";
355 reg = <0x4000000 0x1000>;
356 #clock-cells = <1>;
357 #reset-cells = <1>;
358 #power-domain-cells = <1>;
359 };
360 ...
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