1 # SPDX-License-Identifier: GPL-2.0-only
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sdm845-dispcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Qualcomm Display Clock & Reset Controller on SDM845
8
9 maintainers:
10 - Taniya Das <quic_tdas@quicinc.com>
11
12 description: |
13 Qualcomm display clock control module provides the clocks, resets and power
14 domains on SDM845.
15
16 See also:: include/dt-bindings/clock/qcom,dispcc-sdm845.h
17
18 properties:
19 compatible:
20 const: qcom,sdm845-dispcc
21
22 # NOTE: sdm845.dtsi existed for quite some time and specified no clocks.
23 # The code had to use hardcoded mechanisms to find the input clocks.
24 # New dts files should have these clocks.
25 clocks:
26 items:
27 - description: Board XO source
28 - description: GPLL0 source from GCC
29 - description: GPLL0 div source from GCC
30 - description: Byte clock from DSI PHY0
31 - description: Pixel clock from DSI PHY0
32 - description: Byte clock from DSI PHY1
33 - description: Pixel clock from DSI PHY1
34 - description: Link clock from DP PHY
35 - description: VCO DIV clock from DP PHY
36
37 clock-names:
38 items:
39 - const: bi_tcxo
40 - const: gcc_disp_gpll0_clk_src
41 - const: gcc_disp_gpll0_div_clk_src
42 - const: dsi0_phy_pll_out_byteclk
43 - const: dsi0_phy_pll_out_dsiclk
44 - const: dsi1_phy_pll_out_byteclk
45 - const: dsi1_phy_pll_out_dsiclk
46 - const: dp_link_clk_divsel_ten
47 - const: dp_vco_divided_clk_src_mux
48
49 required:
50 - compatible
51 - clocks
52 - clock-names
53 - '#power-domain-cells'
54
55 allOf:
56 - $ref: qcom,gcc.yaml#
57
58 unevaluatedProperties: false
59
60 examples:
61 - |
62 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
63 #include <dt-bindings/clock/qcom,rpmh.h>
64 clock-controller@af00000 {
65 compatible = "qcom,sdm845-dispcc";
66 reg = <0x0af00000 0x10000>;
67 clocks = <&rpmhcc RPMH_CXO_CLK>,
68 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
69 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
70 <&dsi0_phy 0>,
71 <&dsi0_phy 1>,
72 <&dsi1_phy 0>,
73 <&dsi1_phy 1>,
74 <&dp_phy 0>,
75 <&dp_phy 1>;
76 clock-names = "bi_tcxo",
77 "gcc_disp_gpll0_clk_src",
78 "gcc_disp_gpll0_div_clk_src",
79 "dsi0_phy_pll_out_byteclk",
80 "dsi0_phy_pll_out_dsiclk",
81 "dsi1_phy_pll_out_byteclk",
82 "dsi1_phy_pll_out_dsiclk",
83 "dp_link_clk_divsel_ten",
84 "dp_vco_divided_clk_src_mux";
85 #clock-cells = <1>;
86 #reset-cells = <1>;
87 #power-domain-cells = <1>;
88 };
89 ...
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