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Linux/Documentation/devicetree/bindings/clock/qcom,sdx75-gcc.yaml

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  1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2 %YAML 1.2
  3 ---
  4 $id: http://devicetree.org/schemas/clock/qcom,sdx75-gcc.yaml#
  5 $schema: http://devicetree.org/meta-schemas/core.yaml#
  6 
  7 title: Qualcomm Global Clock & Reset Controller on SDX75
  8 
  9 maintainers:
 10   - Imran Shaik <quic_imrashai@quicinc.com>
 11   - Taniya Das <quic_tdas@quicinc.com>
 12 
 13 description: |
 14   Qualcomm global clock control module provides the clocks, resets and power
 15   domains on SDX75
 16 
 17   See also:: include/dt-bindings/clock/qcom,sdx75-gcc.h
 18 
 19 properties:
 20   compatible:
 21     const: qcom,sdx75-gcc
 22 
 23   clocks:
 24     items:
 25       - description: Board XO source
 26       - description: Sleep clock source
 27       - description: EMAC0 sgmiiphy mac rclk source
 28       - description: EMAC0 sgmiiphy mac tclk source
 29       - description: EMAC0 sgmiiphy rclk source
 30       - description: EMAC0 sgmiiphy tclk source
 31       - description: EMAC1 sgmiiphy mac rclk source
 32       - description: EMAC1 sgmiiphy mac tclk source
 33       - description: EMAC1 sgmiiphy rclk source
 34       - description: EMAC1 sgmiiphy tclk source
 35       - description: PCIE20 phy aux clock source
 36       - description: PCIE_1 Pipe clock source
 37       - description: PCIE_2 Pipe clock source
 38       - description: PCIE Pipe clock source
 39       - description: USB3 phy wrapper pipe clock source
 40 
 41 required:
 42   - compatible
 43   - clocks
 44   - '#power-domain-cells'
 45 
 46 allOf:
 47   - $ref: qcom,gcc.yaml#
 48 
 49 unevaluatedProperties: false
 50 
 51 examples:
 52   - |
 53     #include <dt-bindings/clock/qcom,rpmh.h>
 54     clock-controller@80000 {
 55       compatible = "qcom,sdx75-gcc";
 56       reg = <0x80000 0x1f7400>;
 57       clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, <&emac0_sgmiiphy_mac_rclk>,
 58                <&emac0_sgmiiphy_mac_tclk>, <&emac0_sgmiiphy_rclk>, <&emac0_sgmiiphy_tclk>,
 59                <&emac1_sgmiiphy_mac_rclk>, <&emac1_sgmiiphy_mac_tclk>, <&emac1_sgmiiphy_rclk>,
 60                <&emac1_sgmiiphy_tclk>, <&pcie20_phy_aux_clk>, <&pcie_1_pipe_clk>,
 61                <&pcie_2_pipe_clk>, <&pcie_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
 62       #clock-cells = <1>;
 63       #reset-cells = <1>;
 64       #power-domain-cells = <1>;
 65     };
 66 ...

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