1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm4450-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Qualcomm Global Clock & Reset Controller on SM4450
8
9 maintainers:
10 - Ajit Pandey <quic_ajipan@quicinc.com>
11 - Taniya Das <quic_tdas@quicinc.com>
12
13 description: |
14 Qualcomm global clock control module provides the clocks, resets and power
15 domains on SM4450
16
17 See also:: include/dt-bindings/clock/qcom,sm4450-gcc.h
18
19 properties:
20 compatible:
21 const: qcom,sm4450-gcc
22
23 clocks:
24 items:
25 - description: Board XO source
26 - description: Sleep clock source
27 - description: UFS Phy Rx symbol 0 clock source
28 - description: UFS Phy Rx symbol 1 clock source
29 - description: UFS Phy Tx symbol 0 clock source
30 - description: USB3 Phy wrapper pipe clock source
31
32 required:
33 - compatible
34 - clocks
35 - '#power-domain-cells'
36
37 allOf:
38 - $ref: qcom,gcc.yaml#
39
40 unevaluatedProperties: false
41
42 examples:
43 - |
44 #include <dt-bindings/clock/qcom,rpmh.h>
45 clock-controller@100000 {
46 compatible = "qcom,sm4450-gcc";
47 reg = <0x00100000 0x001f4200>;
48 clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>,
49 <&ufs_mem_phy 0>, <&ufs_mem_phy 1>,
50 <&ufs_mem_phy 2>, <&usb_1_qmpphy>;
51 #clock-cells = <1>;
52 #reset-cells = <1>;
53 #power-domain-cells = <1>;
54 };
55
56 ...
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