1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm6115-dispcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Qualcomm Display Clock Controller for SM6115
8
9 maintainers:
10 - Bjorn Andersson <andersson@kernel.org>
11
12 description: |
13 Qualcomm display clock control module provides the clocks and power domains
14 on SM6115.
15
16 See also:: include/dt-bindings/clock/qcom,sm6115-dispcc.h
17
18 properties:
19 compatible:
20 enum:
21 - qcom,sm6115-dispcc
22
23 clocks:
24 items:
25 - description: Board XO source
26 - description: Board sleep clock
27 - description: Byte clock from DSI PHY0
28 - description: Pixel clock from DSI PHY0
29 - description: GPLL0 DISP DIV clock from GCC
30
31 required:
32 - compatible
33 - clocks
34 - '#power-domain-cells'
35
36 allOf:
37 - $ref: qcom,gcc.yaml#
38
39 unevaluatedProperties: false
40
41 examples:
42 - |
43 #include <dt-bindings/clock/qcom,rpmcc.h>
44 #include <dt-bindings/clock/qcom,gcc-sm6115.h>
45 clock-controller@5f00000 {
46 compatible = "qcom,sm6115-dispcc";
47 reg = <0x5f00000 0x20000>;
48 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
49 <&sleep_clk>,
50 <&dsi0_phy 0>,
51 <&dsi0_phy 1>,
52 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;
53 #clock-cells = <1>;
54 #reset-cells = <1>;
55 #power-domain-cells = <1>;
56 };
57 ...
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